Rtl

Open-source projects categorized as Rtl
Edit details
Language: + Scala + Python + SystemVerilog + Verilog + Objective-C + Swift + C++ + Kotlin + Rust + VHDL + Dart + JavaScript + Ruby
Topics: Verilog Fpga Riscv Systemverilog CSS
The modern identity platform for B2B SaaS
The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.
workos.com
Sponsored

Top 23 Rtl Open-Source Projects

  • MyLinearLayout

    MyLayout is a powerful iOS UI framework implemented by Objective-C. It integrates the functions with Android Layout,iOS AutoLayout,SizeClass, HTML CSS float and flexbox and bootstrap. So you can use LinearLayout,RelativeLayout,FrameLayout,TableLayout,FlowLayout,FloatLayout,PathLayout,GridLayout,LayoutSizeClass to build your App 自动布局 UIView UITableView UICollectionView RTL

  • chisel

    Chisel: A Modern Hardware Design Language (by chipsalliance)

    • Project mention: Calyx: Intermediate Language for Hardware Accelerators | news.ycombinator.com | 2024-02-26

    My first instinct was to ask "Does this play well with CIRCT?" And thankfully they answer that right away in the README.

    I'm personally of the opinion that there is a LOT of room for improvement in the hardware design tooling space, but a combination of market consolidation, huge pressure to meet deadlines, and an existing functional pipeline of Verilog/VHDL talent is preventing changes.

    That's not to say "Verilog/VHDL are bad", because clearly they've been good enough to support nearly all of the wonderful designs powering today's devices. But it is to say, "the startup scene for hardware will continue to look anemic compared to the SaaS scene until someone gives me all of the niceties I have for building SaaS tools in software."

    A huge amount of ideas (and entire designs) start off as software sims, which enables kernel/compiler engineers to start building out support for new hardware before it's manufactured.

    There is some interesting work going on at SiFive building hardware with Chisel[1], as well as some interesting work lead by a professor at William and Mary to improve simulations[2].

    1: https://www.chisel-lang.org

    2: https://github.com/sarchlab/akita

  • InfluxDB

    Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

    InfluxDB logo

  • rocket-chip

    Rocket Chip Generator

  • PinLayout

    Fast Swift Views layouting without auto layout. No magic, pure code, full control and blazing fast. Concise syntax, intuitive, readable & chainable. [iOS/macOS/tvOS/CALayer]

    • Project mention: A lightweight wrapper for lazily initializing UIViews | /r/iOSProgramming | 2023-12-08

  • verilator

    Verilator open-source SystemVerilog simulator and lint system

    • Project mention: What's new for RISC-V in LLVM 17 | news.ycombinator.com | 2023-10-11

    You may want to check out Verilator:

    https://verilator.org/

  • darkriscv

    opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

  • riscv-boom

    SonicBOOM: The Berkeley Out-of-Order Machine

    • Project mention: Is RISC-V ready for HPC? Evaluating the 64-core Sophon SG2042 RISC-V CPU | news.ycombinator.com | 2023-12-10

  • WorkOS

    The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.

    WorkOS logo

  • SpinalHDL

    Scala based HDL

    • Project mention: 1800-2023 – IEEE Standard for SystemVerilog | news.ycombinator.com | 2024-04-17

    I'd love to see textual preprocessors kinda banned. Or at least done upstream and outside of the language. You can't both be and also have a textual preprocessor defined internally. It doesn't work.

    I really like what Zig and C++ are doing with `const`.

    https://ikrima.dev/dev-notes/zig/zig-metaprogramming/

    Have you looked at Spinal?

    https://github.com/SpinalHDL/SpinalHDL

    https://spinalhdl.github.io/SpinalDoc-RTD/master/index.html

  • chipyard

    An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

    • Project mention: Chisel: A Modern Hardware Design Language | news.ycombinator.com | 2023-12-27

    It's probably true that Chisel isn't right for industry -- Google tried it too for the TPU project and eventually went back to Verilog. That said, I think it's main win is that it is great from a research / open-source perspective.

    Taking advantage of the functional nature of Chisel enables a set of generators called Chipyard [0] for things like cores, networking peripherals, neural network accelerators, etc. If you're focusing on exploring the design space of one particular accelerator and don't care too much about the rest of the chip, you can get a customized version of the RTL for the rest of your chip with ease. All the research projects in the lab benefit from code changes to the generators.

    Chisel even enables undergraduate students (like me!) to tape out a chip on a modern-ish process node in just a semester, letting Chisel significantly reduce the amount of RTL we have to write. Most of the remaining time is spent working on the actual physical design process.

    [0]: https://github.com/ucb-bar/chipyard

    [1]: https://classes.berkeley.edu/content/2023-Spring-ELENG-194-0...

  • OpenROAD

    OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

    • Project mention: Importance of Open-Source EDA Tools for Academia | news.ycombinator.com | 2024-03-11

    > [1]: https://theopenroadproject.org/

    All it takes to check your point is to scroll down to the end and follow the link at the bottom of the page to the FOSSI foundation, who hosted this open letter, to realize that they have also developed some widely used EDA tools. Here's a link on case you have missed it

    https://fossi-foundation.org/our-work/projects

  • openlane

    OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

  • axi

    AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

  • Salamandra

    Salamandra is a tool to find spy microphones that use radio freq to transmit. It uses SDR.

  • scr1

    SCR1 is a high-quality open-source RISC-V MCU core in Verilog

  • Cores-VeeR-EH1

    VeeR EH1 core

  • Leku

    :earth_africa: Map location picker component for Android. Based on Google Maps. An alternative to Google Place Picker.

  • riscv-mini

    Simple RISC-V 3-stage Pipeline in Chisel

  • veryl

    Veryl: A Modern Hardware Description Language

    • Project mention: Veryl: A Modern Hardware Description Language | news.ycombinator.com | 2024-03-12

  • bladeRF-wiphy

    bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem

  • pymtl3

    Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

    • Project mention: Firrtl – Flexible Intermediate Representation for RTL | news.ycombinator.com | 2023-07-15

  • rohd

    The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.

    • Project mention: Intel/rohd: Hardware Development framework in the Dart programming language | news.ycombinator.com | 2023-12-27

  • tailwindcss-rtl

    Enabling bidirectional support on tailwindcss framework

  • rggen

    Code generation tool for control and status registers

  • SaaSHub

    SaaSHub - Software Alternatives and Reviews. SaaSHub helps you find the best software and product alternatives

    SaaSHub logo
NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

Rtl related posts

Index

What are some of the best open-source Rtl projects? This list will help you:

Project Stars
1 MyLinearLayout 4,380
2 chisel 3,708
3 rocket-chip 3,011
4 PinLayout 2,289
5 verilator 2,083
6 darkriscv 1,882
7 riscv-boom 1,593
8 SpinalHDL 1,518
9 chipyard 1,428
10 OpenROAD 1,328
11 openlane 1,179
12 axi 922
13 Salamandra 817
14 scr1 775
15 Cores-VeeR-EH1 773
16 Leku 754
17 riscv-mini 493
18 veryl 396
19 bladeRF-wiphy 363
20 pymtl3 348
21 rohd 347
22 tailwindcss-rtl 345
23 rggen 279

Sponsored
SaaSHub - Software Alternatives and Reviews
SaaSHub helps you find the best software and product alternatives
www.saashub.com