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Verilator Alternatives
Similar projects and alternatives to verilator
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HLS-Tiny-Tutorials
This is forked from Xilinx HLS-Tiny-Tutorial. I'm learning HLS and adding Verilator testbench to verify the generated RTL
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WorkOS
The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.
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riscv_vhdl
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
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cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
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sphinxcontrib-hdl-diagrams
Sphinx Extension which generates various types of diagrams from Verilog code.
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Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
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InfluxDB
Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.
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buildit
Online demo without installing at - https://buildit.so/tryit (by BuildIt-lang)
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cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
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verilator reviews and mentions
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What's new for RISC-V in LLVM 17
You may want to check out Verilator:
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Error when running cocotb using cocotb-test
It is 4.106, check https://github.com/verilator/verilator/issues/2778 for more details.
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Verilator: Suggestions for verification framework?
Yeah, there is currently a bug and only one specific version of verilator works with cocotb (4.106). Hopefully it will be fixed soon. Go make noise here: https://github.com/verilator/verilator/issues/2778.
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Vitis HLS and Verilator
Okay, made it. Problem is, that my account is flagged as soon as I created it, I am marked as "spammy", and my "comments will only be shown in staff mode". https://github.com/verilator/verilator/issues/3159
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Systemverilog / verilog functional editor not like vivado
If you will help me with systemverilog black box discusion (I have very low systemverilog experience) and verilator will get update then I will upload on github plugin to Sublime Text which lint whole file every time when you stop typing. Currently I have plugin based on Vivado's compiler, but compilation of simple verilog file takes 1'400ms...
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The FPGA Institute of Technology
Here is the bug report in question: https://github.com/verilator/verilator/issues/2625
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A note from our sponsor - InfluxDB
www.influxdata.com | 28 Mar 2024
Stats
verilator/verilator is an open source project licensed under GNU Lesser General Public License v3.0 only which is an OSI approved license.
The primary programming language of verilator is C++.