Fpga

Open-source projects categorized as Fpga
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Language: + C + Verilog + Python + Java + Assembly + JavaScript + C++ + Scala + Haskell
Topics: Verilog Vhdl Hardware Asic risc-v
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Top 23 Fpga Open-Source Projects

  • john

    John the Ripper jumbo - advanced offline password cracker, which supports hundreds of hash and cipher types, and runs on many operating systems, CPUs, GPUs, and even some FPGAs

    • Project mention: Best Hacking Tools for Beginners 2024 | dev.to | 2024-02-01

    John The Ripper

  • logisim-evolution

    Digital logic design tool and simulator

    • Project mention: Problem with installation | /r/logisim | 2023-07-10

    I have downloaded logisim-evolution from github. While trying to run .msi file, Microsoft Defender blocked it for some reason. I scanned it with some other scanners and everything was fine. I'm not sure if this is safe to install it.

  • InfluxDB

    Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

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  • openwifi

    open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

    • Project mention: Hold on there: WPA3 connections fail after 11 hours | news.ycombinator.com | 2024-01-27

    There is some open source firmware for very old WiFi chips:

    https://wiki.debian.org/Firmware/Open#Radio

    There is also some FPGA based open source WiFi chip things:

    https://github.com/open-sdr/openwifi

  • litex

    Build your hardware, easily!

    • Project mention: FPGA Dev Boards for $150 or Less | news.ycombinator.com | 2023-11-06

    https://github.com/enjoy-digital/litex

    they have tutorials, you can get compatible boards for around $20

  • VexRiscv

    A FPGA friendly 32 bit RISC-V CPU implementation

    • Project mention: Need help to build a RISC-V Processor on Artix-7 FPGA: Final Year Engineering Project Guide | /r/RISCV | 2023-10-23

    With LiteX you can synthesize a VexRiscV processor. You can run Linux on it. The toolchain is pretty easy to use, as long as you use Xilinx Vivado to compile to gateware.

  • cva6

    The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

    • Project mention: CVA6 – an Application class 6-stage RISC-V CPU capable of booting Linux | news.ycombinator.com | 2023-11-15

  • NyuziProcessor

    GPGPU microprocessor architecture

    • Project mention: FuryGpu – Custom PCIe FPGA GPU | news.ycombinator.com | 2024-03-27

    There's also Nyuzi which is more GPGPU focused https://github.com/jbush001/NyuziProcessor, but the author also experimented with having it do 3D graphics.

  • WorkOS

    The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.

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  • darkriscv

    opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

  • glasgow

    Scots Army Knife for electronics

  • icestudio

    :snowflake: Visual editor for open FPGA boards

  • SpinalHDL

    Scala based HDL

    • Project mention: 1800-2023 – IEEE Standard for SystemVerilog | news.ycombinator.com | 2024-04-17

    I'd love to see textual preprocessors kinda banned. Or at least done upstream and outside of the language. You can't both be and also have a textual preprocessor defined internally. It doesn't work.

    I really like what Zig and C++ are doing with `const`.

    https://ikrima.dev/dev-notes/zig/zig-metaprogramming/

    Have you looked at Spinal?

    https://github.com/SpinalHDL/SpinalHDL

    https://spinalhdl.github.io/SpinalDoc-RTD/master/index.html

  • corundum

    Open source FPGA-based NIC and platform for in-network compute

    • Project mention: FuryGpu – Custom PCIe FPGA GPU | news.ycombinator.com | 2024-03-27

    The GPU uses this: https://github.com/alexforencich/verilog-pcie . And there is an open-source 100G NIC here, including open source 10G/25G MACs: https://github.com/corundum/corundum

  • amaranth

    A modern hardware definition language and toolchain based on Python

  • neorv32

    :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

    • Project mention: An example of how to add the A ISA extension's LR/SC operations into an open-source architecture | /r/RISCV | 2023-07-24

  • clash-ghc

    Haskell to VHDL/Verilog/SystemVerilog compiler

    • Project mention: Clash: A Functional Hardware Description Language | news.ycombinator.com | 2023-12-27

  • hdl

    HDL libraries and projects

  • serv

    SERV - The SErial RISC-V CPU

    • Project mention: SERV – The SErial RISC-V CPU | news.ycombinator.com | 2023-12-10

  • Silice

    Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pipelines.

    • Project mention: Unreasonably effective – How video games use LUTs and how you can too | news.ycombinator.com | 2024-02-28

    - how it is computed: https://github.com/sylefeb/Silice/blob/master/projects/ice-v...

    Julia fractal, with a table to do integer multiply! (2.a.b = (a+b)^2 - a^2 - b^2, so just precompute all x^2 in a table! )

  • zipcpu

    A small, light weight, RISC CPU soft core

  • platformio-vscode-ide

    PlatformIO IDE for VSCode: The next generation integrated development environment for IoT

  • fusesoc

    Package manager and build abstraction tool for FPGA/ASIC development

    • Project mention: fusesoc VS vextproj - a user suggested alternative | libhunt.com/r/fusesoc | 2024-03-28

  • TornadoVM

    TornadoVM: A practical and efficient heterogeneous programming framework for managed languages

    • Project mention: Intel Gaudi 3 AI Accelerator | news.ycombinator.com | 2024-04-10

    You don't need to use C++ to interface with CUDA or even write it.

    A while ago NVIDIA and the GraalVM team demoed grCUDA which makes it easy to share memory with CUDA kernels and invoke them from any managed language that runs on GraalVM (which includes JIT compiled Python). Because it's integrated with the compiler the invocation overhead is low:

    https://developer.nvidia.com/blog/grcuda-a-polyglot-language...

    And TornadoVM lets you write kernels in JVM langs that are compiled through to CUDA:

    https://www.tornadovm.org

    There are similar technologies for other languages/runtimes too. So I don't think that will cause NVIDIA to lose ground.

  • hls4ml

    Machine learning on FPGAs using HLS

    • Project mention: How to participate in open-source FPGA projects? | /r/FPGA | 2023-08-04

  • SaaSHub

    SaaSHub - Software Alternatives and Reviews. SaaSHub helps you find the best software and product alternatives

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NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020). The latest post mention was on 2024-04-17.

Fpga related posts

Index

What are some of the best open-source Fpga projects? This list will help you:

Project Stars
1 john 9,231
2 logisim-evolution 4,292
3 openwifi 3,547
4 litex 2,672
5 VexRiscv 2,244
6 cva6 2,074
7 NyuziProcessor 1,900
8 darkriscv 1,873
9 glasgow 1,847
10 icestudio 1,646
11 SpinalHDL 1,506
12 corundum 1,449
13 amaranth 1,431
14 neorv32 1,415
15 clash-ghc 1,370
16 hdl 1,374
17 serv 1,234
18 Silice 1,227
19 zipcpu 1,188
20 platformio-vscode-ide 1,146
21 fusesoc 1,112
22 TornadoVM 1,105
23 hls4ml 1,089

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