|about 1 month ago||6 days ago|
|ISC License||BSD 3-clause "New" or "Revised" License|
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How many LUT for an 8 bit CPU?
2 projects | reddit.com/r/FPGA | 11 Nov 2022
Minimax: a Compressed-First, Microcoded RISC-V CPU
4 projects | reddit.com/r/FPGA | 26 Oct 2022
In short: it works, though the implementation lacks the crystal clarity of FemtoRV32 and PicoRV32. The core is larger than SERV but has higher IPC and (very arguably) a more conventional implementation. The compressed instruction set is easier to expand into regular RV32I instructions than it is to execute directly.
Apple to Move a Part of Its Embedded Cores to RISC-V
4 projects | news.ycombinator.com | 16 Sep 2022
I have created a Reddit community about PicoBlaze soft processor...
2 projects | reddit.com/r/FPGA | 13 Sep 2022
As for the size advantage: this mattered more when LUTs were precious and when PicoBlaze's competition was either similarly unorthodox (J1 Forth CPU) or several times larger (MicroBlaze). Nowadays, there are very small RISC-V cores like FemtoRV32 Quark or SERV. RISC-V benefits from mainstream open-source tooling and has momentum that's hard to beat.
RISC-V announces first new specifications of 2022 adding to 16 ratified in 2021
3 projects | news.ycombinator.com | 21 Jun 2022
The RISC-V spec does allow non-trapping behavior and SeRV in particular has non-trapping behavior, which is an important part of how it can fit into 200 4-input LUTs.
looking for 16 bit RISC ISA to implement on cyclon IV FPGA
2 projects | reddit.com/r/FPGA | 25 Feb 2022
SERV has an RV32I ISA. It is really light. I am sure it will fit.
Risc-v with minimum number of gates
3 projects | reddit.com/r/FPGA | 11 Jan 2022
Olof Kindgren on LinkedIn: We have a new world record! 6000 RISC-V cores in a single chip!
3 projects | reddit.com/r/RISCV | 24 Sep 2021
RISCV sim through Verilator
3 projects | reddit.com/r/FPGA | 29 Aug 2021
I have tested SERV on Verilator. It was working without any problems.
Glacial – microcoded RISC-V core designed for low FPGA resource utilization
3 projects | news.ycombinator.com | 20 Mar 2021
Along the same lines of minimizing the amount of logic used at the cost of cycles, there's SERV which uses a bit-serial implementation with a 1-bit data path: https://github.com/olofk/serv
From time to time, I have been tempted to design a RISC-V implementation out of discrete TTL components. Sure, there are plenty of projects out there to build your own processor from scratch, but most of them aren't LLVM targets!
The 32-bit datapaths and need for so many registers makes it a bit daunting to approach directly. That approach would probably end up similar in scale to a MIPS implementation I once saw done like that. (Can't find the link, but it was about half a dozen A4-sized PCBs).
Retreating to an 8-bit microcoded approach and lifting all the registers and complexity into RAM and software is a very attractive idea. It's not like it would ever be a speed demon, either way.
SUGGEST AN OPEN SOURCE RISC-V CORE DESIGNED IN VERILOG
3 projects | reddit.com/r/RISCV | 26 Nov 2022
GitHub - stnolting/neorv32: 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. this one is good but is written in VHDL though
Anyone want to share some embedded projects they have done?
9 projects | reddit.com/r/embedded | 15 Jul 2022
Maybe not a classic (whatever that means...) project, but I am working (together with others) on a RISC-V microcontroller for FPGAs: https://github.com/stnolting/neorv32
Mapping compressed 'C' instructions to their 32b counterparts.
3 projects | reddit.com/r/RISCV | 30 Jun 2022
Uploading software program to a custom processor design on a Nexys A7
2 projects | reddit.com/r/FPGA | 29 Jun 2022
A tiny and open-source (BSD) RISC-V SoC for (all!) FPGAs
2 projects | reddit.com/r/FPGA | 30 May 2022
Looking for help with RISC-V softcore and VHDL
3 projects | reddit.com/r/FPGA | 20 Apr 2022
Risc-v rv32i softcore processor for Zybo-z7-10
4 projects | reddit.com/r/FPGA | 14 Apr 2022
How about the NEORV32?
RISC-V Verilog tutorials
2 projects | reddit.com/r/RISCV | 28 Feb 2022
This VHDL RISC-V SoC has a lot of documentation: https://github.com/stnolting/neorv32
How to verify Embench Benchmark in a RISC-V core?
2 projects | reddit.com/r/RISCV | 14 Feb 2022
I am not sure about Embench, but you could start with "porting" CoreMark as there are several implementations out there (like this one).2 projects | reddit.com/r/RISCV | 14 Feb 2022
This highly depends on your RISC-V system. If you already have a UART you can use that to output data via printf (for example using newlib's system calls). But in most cases is pretty oversized as it requires 100s of kB of memory. I think it would be better to use some kind of "embedded printf" like this from the example provided above and just add the according "putc" function to send one char to your UART.
What are some alternatives?
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
linux-on-litex-vexriscv - Linux on LiteX-VexRiscv
picoMIPS - picoMIPS processor doing affine transformation
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
fpga-zynq - Support for Rocket Chip on Zynq FPGAs
linux-on-litex-rocket - Run 64-bit Linux on LiteX + RocketChip
wb2axip - Bus bridges and other odds and ends
riscv-cores-list - RISC-V Cores, SoC platforms and SoCs
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
openFPGALoader - Universal utility for programming FPGA