biriscv VS open-register-design-tool

Compare biriscv vs open-register-design-tool and see what are their differences.

biriscv

32-bit Superscalar RISC-V CPU (by ultraembedded)
risc-v Rv32i Rv32im Superscalar Cpu Fpga Verilog pipelined-processors Verilator Coremark Asic branch-prediction in-order Linux riscv-linux Xilinx artix-7
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open-register-design-tool

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input (by Juniper)
systemrdl jspec eda Asic Fpga registers Uvm Systemverilog register-descriptions systemrdl-compiler
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biriscv open-register-design-tool
6 2
749 181
- 2.2%
0.0 5.3
over 2 years ago 9 months ago
Verilog Verilog
Apache License 2.0 Apache License 2.0
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
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biriscv

Posts with mentions or reviews of biriscv. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-06-21.

open-register-design-tool

Posts with mentions or reviews of open-register-design-tool. We have used some of these posts to build our list of alternatives and similar projects.
  • Thoughts about SystemRDL ?
    1 project | /r/FPGA | 8 Mar 2021
    I have used this compiler (https://github.com/Juniper/open-register-design-tool/wiki/Running-Ordt) to generate a Python model to access registers (I use Python on embedded Linux to read/write registers over SPI to the device).
  • Auto Generate Header Files
    1 project | /r/FPGA | 28 Jan 2021

What are some alternatives?

When comparing biriscv and open-register-design-tool you can also consider the following projects:

riscv - RISC-V CPU Core (RV32IM)

rggen - Code generation tool for control and status registers

darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

livehd - Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

sdspi - SD-Card controller, using either SPI, SDIO, or eMMC interfaces

gf180mcu-pdk - PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).

zipcpu - A small, light weight, RISC CPU soft core

PeakRDL-html - Generate address space documentation HTML from compiled SystemRDL input

vgasim - A Video display simulator

OpenTimer - A High-performance Timing Analysis Tool for VLSI Systems

wbicapetwo - Wishbone to ICAPE interface conversion

openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

biriscv vs riscv open-register-design-tool vs rggen biriscv vs darkriscv open-register-design-tool vs livehd biriscv vs sdspi open-register-design-tool vs gf180mcu-pdk biriscv vs zipcpu open-register-design-tool vs PeakRDL-html biriscv vs vgasim open-register-design-tool vs OpenTimer biriscv vs wbicapetwo open-register-design-tool vs openlane