open-register-design-tool
openlane
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open-register-design-tool | openlane | |
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2 | 12 | |
181 | 1,174 | |
2.2% | 4.8% | |
5.3 | 8.6 | |
9 months ago | 6 days ago | |
Verilog | Python | |
Apache License 2.0 | Apache License 2.0 |
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open-register-design-tool
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Thoughts about SystemRDL ?
I have used this compiler (https://github.com/Juniper/open-register-design-tool/wiki/Running-Ordt) to generate a Python model to access registers (I use Python on embedded Linux to read/write registers over SPI to the device).
- Auto Generate Header Files
openlane
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[D][P] Represent Analog Circuits as Graphs
I would suggest Verilog-to-routing as the best open source tool ive used that deals with abstract circuit representations on an FPGA or similar architecture. but tools like Align and Magical both accept circuit inputs as netlists and have to represent them internally for generating layout so might be easier to understand their approach depending on your familiarity with analog circuits. One more option is to look up OpenLane flow, its more an amalgamation of lots of tools but definitely also represents circuits as a graph for manipulation later on.
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how small team survive from cadence cost
There are open source alternatives. https://github.com/The-OpenROAD-Project/OpenLane
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VLSI Tools
OpenLane
- Compiling Code into Silicon
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Kickstarting IC design
And, there is a project called 'The OpenROAD Project' which has created an open-source framework for digital back-end design/physical design. https://github.com/The-OpenROAD-Project/OpenLane
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How are modern processors and their architecture designed?
For "how the architecture is brought to silicon": Look at OpenLane. It's a complete Verilog to GDS flow, all open source and already used for some tape-outs. https://github.com/The-OpenROAD-Project/OpenLane
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Project Ideas for Uni
Maybe you can do something that can also go to an ASIC. Take a look at openlane flow, you don't need to do the backend since it is mostly script based and you can even send it to next Skywater submission. The major problem is that you currently don't have sram access so you need to create rams from logic if you need to.
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ASIC design post layout for padding.
I am not sure if you can do padding with this but dropping this down in case you haven't heard it: https://github.com/The-OpenROAD-Project/OpenLane
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Resources for a physical design engineer
Specifically openlane (https://github.com/The-OpenROAD-Project/OpenLane is a great way to start, although it's very painful trying to do complex designs. However, they're pretty helpful answering questions on Gitter
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Intro into chip design
https://github.com/efabless/openlane The README is very helpful
What are some alternatives?
rggen - Code generation tool for control and status registers
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
livehd - Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
picorv32 - PicoRV32 - A Size-Optimized RISC-V CPU
gf180mcu-pdk - PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).
freepdk-45nm - ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
PeakRDL-html - Generate address space documentation HTML from compiled SystemRDL input
rocket-chip - Rocket Chip Generator
OpenTimer - A High-performance Timing Analysis Tool for VLSI Systems
NTHU-ICLAB - 清華大學 | 積體電路設計實驗 (IC LAB) | 110上
biriscv - 32-bit Superscalar RISC-V CPU
riscv - RISC-V CPU Core (RV32IM)