FPGA_Asynchronous_FIFO
FIFO implementation with different clock domains for read and write. (by AngeloJacobo)
darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night! (by darklife)
| FPGA_Asynchronous_FIFO | darkriscv | |
|---|---|---|
| 1 | 3 | |
| 10 | 1,897 | |
| - | 1.7% | |
| 0.0 | 6.3 | |
| over 2 years ago | 18 days ago | |
| Verilog | Verilog | |
| MIT License | BSD 3-clause "New" or "Revised" License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
FPGA_Asynchronous_FIFO
Posts with mentions or reviews of FPGA_Asynchronous_FIFO.
We have used some of these posts to build our list of alternatives
and similar projects.
darkriscv
Posts with mentions or reviews of darkriscv.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-08-20.
-
As an undergrad in my 3rd year with what feels like very little basics down, is implementing a basic RISC-V 5-stage pipelined processor on an FPGA too complex a project for an undergrad student?
This guy here has designed his 2 stage RISC-V in just one right: https://github.com/darklife/darkriscv.
- Are there any dual-GBE, PoE-capable SBCs?
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Chinese Academy of Sciences releases "Xiangshan", a high performance open source RISC-V processor that runs Linux
Just found https://github.com/darklife/darkriscv whose (incomplete) core is surprisingly short. Which means you won't have to learn a lot. You can run it in simulator or on one of the listed fpga boards.
What are some alternatives?
When comparing FPGA_Asynchronous_FIFO and darkriscv you can also consider the following projects:
zipcpu - A small, light weight, RISC CPU soft core
biriscv - 32-bit Superscalar RISC-V CPU
open-fpga-verilog-tutorial - Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
XiangShan - Open-source high-performance RISC-V processor
riscv - RISC-V CPU Core (RV32IM)
serv - SERV - The SErial RISC-V CPU
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
hdl - HDL libraries and projects
Cores-VeeR-EH1 - VeeR EH1 core
friscv - RISCV CPU implementation in SystemVerilog
meta-riscv - OpenEmbedded/Yocto layer for RISC-V Architecture
FPGA_Asynchronous_FIFO vs zipcpu
darkriscv vs biriscv
FPGA_Asynchronous_FIFO vs open-fpga-verilog-tutorial
darkriscv vs XiangShan
FPGA_Asynchronous_FIFO vs biriscv
darkriscv vs riscv
FPGA_Asynchronous_FIFO vs serv
darkriscv vs VexRiscv
FPGA_Asynchronous_FIFO vs hdl
darkriscv vs Cores-VeeR-EH1
darkriscv vs friscv
darkriscv vs meta-riscv