Verilog

Open-source projects categorized as Verilog
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Language: + Verilog + C + Python + Scala + C++ + JavaScript + Java + Assembly + Haskell + SystemVerilog
Topics: Fpga Vhdl Systemverilog risc-v Hdl
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Top 23 Verilog Open-Source Projects

  • logisim-evolution

    Digital logic design tool and simulator

    • Project mention: Problem with installation | /r/logisim | 2023-07-10

    I have downloaded logisim-evolution from github. While trying to run .msi file, Microsoft Defender blocked it for some reason. I scanned it with some other scanners and everything was fine. I'm not sure if this is safe to install it.

  • chisel

    Chisel: A Modern Hardware Design Language (by chipsalliance)

    • Project mention: Calyx: Intermediate Language for Hardware Accelerators | news.ycombinator.com | 2024-02-26

    My first instinct was to ask "Does this play well with CIRCT?" And thankfully they answer that right away in the README.

    I'm personally of the opinion that there is a LOT of room for improvement in the hardware design tooling space, but a combination of market consolidation, huge pressure to meet deadlines, and an existing functional pipeline of Verilog/VHDL talent is preventing changes.

    That's not to say "Verilog/VHDL are bad", because clearly they've been good enough to support nearly all of the wonderful designs powering today's devices. But it is to say, "the startup scene for hardware will continue to look anemic compared to the SaaS scene until someone gives me all of the niceties I have for building SaaS tools in software."

    A huge amount of ideas (and entire designs) start off as software sims, which enables kernel/compiler engineers to start building out support for new hardware before it's manufactured.

    There is some interesting work going on at SiFive building hardware with Chisel[1], as well as some interesting work lead by a professor at William and Mary to improve simulations[2].

    1: https://www.chisel-lang.org

    2: https://github.com/sarchlab/akita

  • InfluxDB

    Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

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  • openwifi

    open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

    • Project mention: Hold on there: WPA3 connections fail after 11 hours | news.ycombinator.com | 2024-01-27

    There is some open source firmware for very old WiFi chips:

    https://wiki.debian.org/Firmware/Open#Radio

    There is also some FPGA based open source WiFi chip things:

    https://github.com/open-sdr/openwifi

  • VexRiscv

    A FPGA friendly 32 bit RISC-V CPU implementation

    • Project mention: Need help to build a RISC-V Processor on Artix-7 FPGA: Final Year Engineering Project Guide | /r/RISCV | 2023-10-23

    With LiteX you can synthesize a VexRiscV processor. You can run Linux on it. The toolchain is pretty easy to use, as long as you use Xilinx Vivado to compile to gateware.

  • verilator

    Verilator open-source SystemVerilog simulator and lint system

    • Project mention: What's new for RISC-V in LLVM 17 | news.ycombinator.com | 2023-10-11

    You may want to check out Verilator:

    https://verilator.org/

  • NyuziProcessor

    GPGPU microprocessor architecture

    • Project mention: Tiny GPU: A minimal GPU implementation in Verilog | news.ycombinator.com | 2024-04-24

    Nice! I warmly encourage open-core GPU work.

    Here's another: https://github.com/jbush001/NyuziProcessor

  • darkriscv

    opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

  • WorkOS

    The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.

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  • icestudio

    :snowflake: Visual editor for open FPGA boards

  • cocotb

    cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

    • Project mention: Designing a Low Latency 10G Ethernet Core | /r/FPGA | 2023-07-04

    The use of cocotb and pyuvm for verification

  • SpinalHDL

    Scala based HDL

    • Project mention: 1800-2023 – IEEE Standard for SystemVerilog | news.ycombinator.com | 2024-04-17

    I'd love to see textual preprocessors kinda banned. Or at least done upstream and outside of the language. You can't both be and also have a textual preprocessor defined internally. It doesn't work.

    I really like what Zig and C++ are doing with `const`.

    https://ikrima.dev/dev-notes/zig/zig-metaprogramming/

    Have you looked at Spinal?

    https://github.com/SpinalHDL/SpinalHDL

    https://spinalhdl.github.io/SpinalDoc-RTD/master/index.html

  • neorv32

    :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

    • Project mention: An example of how to add the A ISA extension's LR/SC operations into an open-source architecture | /r/RISCV | 2023-07-24

  • hdl

    HDL libraries and projects

  • clash-ghc

    Haskell to VHDL/Verilog/SystemVerilog compiler

    • Project mention: Clash: A Functional Hardware Description Language | news.ycombinator.com | 2023-12-27

  • OpenROAD

    OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

    • Project mention: Importance of Open-Source EDA Tools for Academia | news.ycombinator.com | 2024-03-11

    > [1]: https://theopenroadproject.org/

    All it takes to check your point is to scroll down to the end and follow the link at the bottom of the page to the FOSSI foundation, who hosted this open letter, to realize that they have also developed some widely used EDA tools. Here's a link on case you have missed it

    https://fossi-foundation.org/our-work/projects

  • serv

    SERV - The SErial RISC-V CPU

    • Project mention: SERV – The SErial RISC-V CPU | news.ycombinator.com | 2023-12-10

  • zipcpu

    A small, light weight, RISC CPU soft core

  • openlane

    OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

  • platformio-vscode-ide

    PlatformIO IDE for VSCode: The next generation integrated development environment for IoT

  • fusesoc

    Package manager and build abstraction tool for FPGA/ASIC development

    • Project mention: fusesoc VS vextproj - a user suggested alternative | libhunt.com/r/fusesoc | 2024-03-28

  • metroboy

    A repository of gate-level simulators and tools for the original Game Boy.

    • Project mention: When would you ever want bubblesort? | news.ycombinator.com | 2023-12-05

    He wrote a game engine, it renders transparent items using the painter's algorithm, which requires the items to be sorted in Z. He has a routine that iterates over all items to render them, and bubble-sorts the items in-place while iterating over the items (all in the same thread). The "compare and swap" in this case is the innermost functionality of bubblesort.

    I assume the author is https://github.com/aappleby but I don't see any obvious candidate for this code. Maybe this? https://github.com/aappleby/metroboy but I can't see why a gate-level emulator woudl need to render transparent items using painter's algorithm.

  • riscv

    RISC-V CPU Core (RV32IM)

    • Project mention: Ultraembedded RISCV Module | /r/RISCV | 2023-08-04

    I have been trying to execute some instructions to the ultraembedded riscv module https://github.com/ultraembedded/riscv

  • awesome-hdl

    Hardware Description Languages

  • scr1

    SCR1 is a high-quality open-source RISC-V MCU core in Verilog

  • SaaSHub

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NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

Verilog related posts

Index

What are some of the best open-source Verilog projects? This list will help you:

Project Stars
1 logisim-evolution 4,307
2 chisel 3,708
3 openwifi 3,558
4 VexRiscv 2,252
5 verilator 2,083
6 NyuziProcessor 1,916
7 darkriscv 1,882
8 icestudio 1,650
9 cocotb 1,599
10 SpinalHDL 1,518
11 neorv32 1,423
12 hdl 1,378
13 clash-ghc 1,372
14 OpenROAD 1,328
15 serv 1,244
16 zipcpu 1,190
17 openlane 1,174
18 platformio-vscode-ide 1,151
19 fusesoc 1,115
20 metroboy 1,089
21 riscv 1,040
22 awesome-hdl 871
23 scr1 775

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