Top 23 Hdl Open-Source Projects

• amaranth

  7 1,436 9.7 Python

  A modern hardware definition language and toolchain based on Python

  

• hdl

  5 1,378 9.1 Verilog

  HDL libraries and projects

  

• InfluxDB

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  Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

  

• metroboy

  19 1,089 6.7 C++

  A repository of gate-level simulators and tools for the original Game Boy.

Project mention: When would you ever want bubblesort? | news.ycombinator.com | 2023-12-05

He wrote a game engine, it renders transparent items using the painter's algorithm, which requires the items to be sorted in Z. He has a routine that iterates over all items to render them, and bubble-sorts the items in-place while iterating over the items (all in the same thread). The "compare and swap" in this case is the innermost functionality of bubblesort.

I assume the author is https://github.com/aappleby but I don't see any obvious candidate for this code. Maybe this? https://github.com/aappleby/metroboy but I can't see why a gate-level emulator woudl need to render transparent items using painter's algorithm.

• awesome-hdl

  1 875 4.4

  Hardware Description Languages

• nmigen

  3 643 1.8 Python

  A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen

  

• bladeRF-wiphy

  2 363 0.0 VHDL

  bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem

  

• pymtl3

  5 350 4.6 Python

  Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

  

Project mention: Firrtl – Flexible Intermediate Representation for RTL | news.ycombinator.com | 2023-07-15

• SaaSHub

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• rohd

  8 350 8.0 Dart

  The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.

  

Project mention: Intel/rohd: Hardware Development framework in the Dart programming language | news.ycombinator.com | 2023-12-27

• tensil

  12 319 0.0 Scala

  Open source machine learning accelerators

  

Project mention: Tensil | news.ycombinator.com | 2023-06-22

• VeloView

  1 313 2.6 C++

  VeloView performs real-time visualization and easy processing of live captured 3D LiDAR data from Velodyne sensors (Alpha Prime™, Puck™, Ultra Puck™, Puck Hi-Res™, Alpha Puck™, Puck LITE™, HDL-32, HDL-64E). Runs on Windows, Linux and MacOS. This repository is a mirror of https://gitlab.kitware.com/LidarView/VeloView-Velodyne.

  

• surf

  1 285 8.7 VHDL

  A huge VHDL library for FPGA development (by slaclab)

  

• reviews

  1 263 7.9 JavaScript

  Reviewing some online CS courses I took (by spamegg1)

• f4pga-arch-defs

  19 248 7.7 Jupyter Notebook

  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

  

• livehd

  1 197 9.2 Verilog

  Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

  

• hdl_checker

  4 183 0.0 Python

  Repurposing existing HDL tools to help writing better code

• metron

  15 151 9.6 C++

  A C++ to Verilog translation tool with some basic guarantees that your code will work. (by aappleby)

• cpu11

  2 147 5.3 Verilog

  Revengineered ancient PDP-11 CPUs, originals and clones

• pygears

  5 143 0.0 Python

  HW Design: A Functional Approach

• gateware-ts

  1 97 10.0 TypeScript

  Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

  

Project mention: Chisel: A Modern Hardware Design Language | news.ycombinator.com | 2023-12-27

I figured this must exist and indeed: https://github.com/gateware-ts/gateware-ts

• DFHDL

  1 66 0.0 Scala

  DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language

  

• BrianHG-DDR3-Controller

  2 60 10.0 SystemVerilog

  DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

• sphinxcontrib-hdl-diagrams

  2 50 5.7 Python

  Sphinx Extension which generates various types of diagrams from Verilog code.

  

• cocotb-bus

  1 46 3.7 Python

  Pre-packaged testbenching tools and reusable bus interfaces for cocotb

  

• SaaSHub

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Hdl related posts

• Chisel: A Modern Hardware Design Language

  6 projects | news.ycombinator.com | 27 Dec 2023

• Intel/rohd: Hardware Development framework in the Dart programming language

  1 project | news.ycombinator.com | 27 Dec 2023

• Timing diagram help

  2 projects | /r/FPGA | 1 Mar 2023

• Building a HDL (Kind of)

  1 project | /r/FPGA | 2 Dec 2022

• Why are there only 3 languages for FPGA development?

  5 projects | /r/FPGA | 1 Dec 2022

• Discussion Thread

  2 projects | /r/neoliberal | 1 Oct 2022

• Choice of Python HDL library

  10 projects | /r/FPGA | 25 Jul 2022
• A note from our sponsor - SaaSHub
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