surf VS axi

Compare surf vs axi and see what are their differences.

surf

A huge VHDL library for FPGA development (by slaclab)
Asic Firmware Fpga Hdl Python Vhdl
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axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication (by pulp-platform)
axi Axi4 axi4-lite Systemverilog Hardware network-on-chip Asic Fpga Rtl IP
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surf axi
1 3
285 930
1.1% 3.0%
8.7 6.1
8 days ago 3 days ago
VHDL SystemVerilog
GNU General Public License v3.0 or later GNU General Public License v3.0 or later
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

surf

Posts with mentions or reviews of surf. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-11-18.

axi

Posts with mentions or reviews of axi. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-06-28.

What are some alternatives?

When comparing surf and axi you can also consider the following projects:

satcat5 - SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.

chisel - Chisel: A Modern Hardware Design Language

nmigen - A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen

tiny-cores - Collection of assorted small cores

fusesoc - Package manager and build abstraction tool for FPGA/ASIC development

basejump_stl - BaseJump STL: A Standard Template Library for SystemVerilog

opentitan - OpenTitan: Open source silicon root of trust

fusesoc-cores - FuseSoC standard core library

qemu - Xilinx's fork of Quick EMUlator (QEMU) with improved support and modelling for the Xilinx platforms.

Pyverilog - Python-based Hardware Design Processing Toolkit for Verilog HDL

surf vs satcat5 axi vs chisel surf vs chisel axi vs nmigen surf vs tiny-cores axi vs fusesoc surf vs basejump_stl axi vs opentitan surf vs fusesoc-cores axi vs qemu surf vs fusesoc axi vs Pyverilog