riscv-boom
Cores-VeeR-EH1
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riscv-boom | Cores-VeeR-EH1 | |
---|---|---|
12 | 8 | |
1,593 | 773 | |
3.0% | 1.6% | |
7.2 | 0.0 | |
about 1 month ago | 11 months ago | |
Scala | SystemVerilog | |
BSD 3-clause "New" or "Revised" License | Apache License 2.0 |
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riscv-boom
- Is RISC-V ready for HPC? Evaluating the 64-core Sophon SG2042 RISC-V CPU
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Cascade: CPU Fuzzing via Intricate Program Generation
Looks like from Appendix D that only 2 bugs were found in BOOM:
> 1. Inaccurate instruction count when minstret is written by software
I don't know what that means, but having minstret written by software was definitely not something I ever tested. In general, perf counters are likely to be undertested.
> 2. Static rounding is ignored for fdiv.s and fsqrt.s
A mistake was made in only listening to the dynamic rounding mode for the fdiv/sqrt unit. This is one of those bugs that is trivially found if you test for it, but it turns out that no benchmarking ever cared about this and from all of the fuzzers I used when I worked on BOOM, NONE of them hit it (including commercial ones...). Ooops.
Fixed here: https://github.com/riscv-boom/riscv-boom/pull/629/files
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In your opinion, what is the most advanced open source softcore processor?
The two most micro architecturally advanced cores that I know of are BOOM, an out of order RV64GC core with all the features you expect plus sort of weird fancy things like short forward branch predication, and VROOM, another out of order RV64GC core with things like uop fusion and a trace cache.
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PyXHDL - Python Frontend For VHDL And Verilog
it is used in the Berkley Out-of-Order RISC-V processor: https://github.com/riscv-boom/riscv-boom
- Semidynamics Unveils First Customizable RISC-V Cores for End Users
- TechTechPotato (Dr Ian Cutress): "Building High-Performance RISC-V Cores for Everything"
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Open-source RISC-V CPU projects for contribution
SonicBOOM: https://github.com/riscv-boom/riscv-boom
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The Surprising Subtleties of Zeroing a Register
Some cores are open source and you can see for yourself.
Rename logic from BOOM, a RISC-V core written in a DSL embedded in Scala:
https://github.com/riscv-boom/riscv-boom/blob/1ef2bc6f6c98e5...
From RSD, a core designed for FPGAs written in SystemVerilog:
https://github.com/rsd-devel/rsd/blob/master/Processor/Src/R...
And then there's the recently open-sourced XuanTie C910, which contains this Verilog… which is completely unreadable. Seems like it was produced by some kind of code generator that they didn't open-source?
https://github.com/T-head-Semi/openc910/blob/d4a3b947ec9bb8f...
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Anandtech: "IBM Power10 Coming To Market: E1080 for 'Frictionless Hybrid Cloud Experiences'"
We don't have Sifive's specifically but we do have the open source cores they've historically used to design their cores: https://github.com/riscv-boom/riscv-boom https://github.com/chipsalliance/rocket-chip
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Fence instruction implementation in BOOM
If you look at the decoder (https://github.com/riscv-boom/riscv-boom/blob/master/src/main/scala/exu/decode.scala), you can see that the fence instructions are also marked as "unique" instructions. Only one "unique" instruction is allowed in the pipeline at a time.
Cores-VeeR-EH1
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Looking for a RISC-V core for verification
SweRV EH1 comes with a verilator testbench that can run compiled instructions. You'll need to expand on it if you want things like external memory etc.
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Nvidia: GPUs can do better chip design in a few days than 10 man year
together foundations and the use domains of chip design, networks and robotics; (iii) the cycle of translation and impact brings research and the leading edge of practice closer together; and (iv) the cycle of research, education, and broadening participation grows the field and its workforce.*
The virtues written here are self evident & obvious. Trying to just get good yourself without trying to help advance the field, not participating, not taking advantages of scale of many working together, not participating in open research, the risks of having isolated teams, and not participating in cycles of development: whatever the nvidia or "publicly traded company" worlds think they're doing, they're missing out, and hurting everyone and especially themselves for this oldschool zero-sum competitive thinking.
There are plenty of company's releasing the chips too. Google's OpenTitan[2] security chip. WD's Swerv RISC-V core for their driver controller ARM R-series replacement[3]. Open standards if not chips like UCI for chiplets or CXL for interconnect are again examples of literally everyone but NVidia playing well together, trying for better, standardizing a future for participation & healthy competition & growth. Nvidia again and again is the company which simply will not play with others.
I challenge you to answer your own question in reverse: are any companies other than Nvidia embarking up AI/ML chipmaking in a closed fashion? There probably are, let's follow & watch them.
[1] https://theopenroadproject.org/news/leveling-up-a-trajectory...
[2] https://opentitan.org/
[3] https://github.com/chipsalliance/Cores-SweRV
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Is a single cycle CPU of any use besides learning?
Absolutely! I have no illusions that I'll build anything even remotely comparable to a commercial core. I had a look at the features of the WD SweRV core and the complexity simply blows my mind, I don't think I'll get there any time soon. This is purely for fun, but it will be much more satisfying if I can start using the CPU I designed in my tiny personal IoT projects. Hence the question, at what point can I start finding some use for it. Maybe an arduino replacement?
- How does philosophy of open source hardware react to "dominant" chip makers?
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Anandtech: "IBM Power10 Coming To Market: E1080 for 'Frictionless Hybrid Cloud Experiences'"
Including Western Digital's cores used in their SSD controllers: https://github.com/chipsalliance/Cores-SweRV https://github.com/chipsalliance/Cores-SweRV-EL2
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Nvidia's ownership of ARM could drive customers to RISC-V, other alternatives if not careful, says Xilinx CEO
This act is probably the single biggest driver of immediate term adoption of RISC-V. Western Digital creating their own RISC-V chip and open sourcing it hurt either.
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About RISC-V becoming so popular as ARM for Embedded Systems
Per your last point, I believe this is the most important one. Big vendors like WD can just design their own core and plop it down in all of their hard drives that ship in large volumes. They even share their RTL.
What are some alternatives?
rocket-chip - Rocket Chip Generator
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
openc910 - OpenXuantie - OpenC910 Core
Cores-VeeR-EL2 - VeeR EL2 Core
XiangShan - Open-source high-performance RISC-V processor
rsd - RSD: RISC-V Out-of-Order Superscalar Processor
RISC-V-Guide - RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.
riscv-mini - Simple RISC-V 3-stage Pipeline in Chisel
cv32e40p - CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
riscv-cores-list - RISC-V Cores, SoC platforms and SoCs