riscv-boom VS openc910

Looks like from Appendix D that only 2 bugs were found in BOOM:

> 1. Inaccurate instruction count when minstret is written by software

I don't know what that means, but having minstret written by software was definitely not something I ever tested. In general, perf counters are likely to be undertested.

> 2. Static rounding is ignored for fdiv.s and fsqrt.s

A mistake was made in only listening to the dynamic rounding mode for the fdiv/sqrt unit. This is one of those bugs that is trivially found if you test for it, but it turns out that no benchmarking ever cared about this and from all of the fuzzers I used when I worked on BOOM, NONE of them hit it (including commercial ones...). Ooops.

Fixed here: https://github.com/riscv-boom/riscv-boom/pull/629/files

The two most micro architecturally advanced cores that I know of are BOOM, an out of order RV64GC core with all the features you expect plus sort of weird fancy things like short forward branch predication, and VROOM, another out of order RV64GC core with things like uop fusion and a trace cache.

it is used in the Berkley Out-of-Order RISC-V processor: https://github.com/riscv-boom/riscv-boom

SonicBOOM: https://github.com/riscv-boom/riscv-boom

Some cores are open source and you can see for yourself.

Rename logic from BOOM, a RISC-V core written in a DSL embedded in Scala:

https://github.com/riscv-boom/riscv-boom/blob/1ef2bc6f6c98e5...

From RSD, a core designed for FPGAs written in SystemVerilog:

https://github.com/rsd-devel/rsd/blob/master/Processor/Src/R...

And then there's the recently open-sourced XuanTie C910, which contains this Verilog… which is completely unreadable. Seems like it was produced by some kind of code generator that they didn't open-source?

https://github.com/T-head-Semi/openc910/blob/d4a3b947ec9bb8f...

We don't have Sifive's specifically but we do have the open source cores they've historically used to design their cores: https://github.com/riscv-boom/riscv-boom https://github.com/chipsalliance/rocket-chip

If you look at the decoder (https://github.com/riscv-boom/riscv-boom/blob/master/src/main/scala/exu/decode.scala), you can see that the fence instructions are also marked as "unique" instructions. Only one "unique" instruction is allowed in the pipeline at a time.

> I'm pretty sure that SiFive isn't allowed to sell their RISC-V core designs to any Chinese company already.

The JH7110 SoC from the Chinese firm Starfive uses SiFive's U74 core. Eswin, also Chinese uses SiFive's P550 core in their upcoming EIC7700 SoC.

> All Chinese RISC-V core designs have been proprietary designs thus far.

There is the OpenC910 [1] and OpenXiangShan [2].

[1] https://github.com/T-head-Semi/openc910

Note that the C910 CPU cores used in this chip are in fact open source:

https://github.com/T-head-Semi/openc910

(C920 is just C910 plus RVV draft 0.7.1 vector unit which pretty much no software uses anyway, sadly)

The Milk-V Pioneer uses a C910 CPU, which has been open sourced by t-head: https://github.com/T-head-Semi/openc910

More precisely, a Chinese university assembled a rack containing 48 [1] commercially available SBCs [2], each with a Chinese-designed and made SG2042 SoC with 64 C910 CPU cores. The C910 was designed in China in 2018/19 and open-sourced in October 2021, on Microsoft's github site.

https://github.com/T-head-Semi/openc910

The SG2042 is the most powerful RISC-V SoC available today.

In which direction is the technology transfer going?

[1] or possibly 24 dual-socket boards, shown at the RISC-V Summit China in August

[2] get your own here https://www.crowdsupply.com/milk-v/milk-v-pioneer

For "coming down the pipeline" they're essentially free.

Today, the c910 is an Apache 2, hardware proven out of order core on GitHub here https://github.com/T-head-Semi/openc910 a little slower than an RPi3's core.

Here is the source code* for the CPU:

https://github.com/T-head-Semi/openc910

* AFAIK they didn't opensource the pre ratification vector extension implementation they ship with the taped out chip.

The source RTL for the roughly Arm A72-equivalent cores used in this were open-sourced several years ago.

https://github.com/T-head-Semi/openc910

The same cores are used in the 64 core SG2042 workstation/server SoC.

It's a shame, because it was the best design from ARM; they're now focusing on Cortex-A7x and Cortex-X, which aren't anywhere as power efficient[0].

Meanwhile, their revised Cortex-A57 has been surpassed in performance/power/area by several RISC-V microarchitectures, such as SiFive's U74[1], used in the VisionFive2 and Star64, or even the open source XuanTie C910[2][3].

0. https://www.youtube.com/watch?v=s0ukXDnWlTY

1. https://www.sifive.com/cores/u74

2. https://xrvm.com/cpu-details?id=4056743610438262784

3. https://github.com/T-head-Semi/openc910