cheshire VS axi

Compare cheshire vs axi and see what are their differences.

cheshire

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6 (by pulp-platform)
Fpga Riscv rtl-design Simulation Systemverilog Asic
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axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication (by pulp-platform)
axi Axi4 axi4-lite Systemverilog Hardware network-on-chip Asic Fpga Rtl IP
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cheshire axi
1 3
107 930
10.3% 3.0%
7.6 6.1
3 days ago 9 days ago
SystemVerilog SystemVerilog
GNU General Public License v3.0 or later GNU General Public License v3.0 or later
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

cheshire

Posts with mentions or reviews of cheshire. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-05-08.
  • Cpu project
    2 projects | /r/RISCV | 8 May 2023
    If you want to see the difference in scale you may want to compare the Cheshire SoC (Linux capable) here

axi

Posts with mentions or reviews of axi. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-06-28.

What are some alternatives?

When comparing cheshire and axi you can also consider the following projects:

hdmi - Send video/audio over HDMI on an FPGA

chisel - Chisel: A Modern Hardware Design Language

friscv - RISCV CPU implementation in SystemVerilog

nmigen - A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen

pulpissimo - This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

fusesoc - Package manager and build abstraction tool for FPGA/ASIC development

rp32 - RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).

opentitan - OpenTitan: Open source silicon root of trust

libsv - An open source, parameterized SystemVerilog digital hardware IP library

qemu - Xilinx's fork of Quick EMUlator (QEMU) with improved support and modelling for the Xilinx platforms.

cva6 - The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Pyverilog - Python-based Hardware Design Processing Toolkit for Verilog HDL

cheshire vs hdmi axi vs chisel cheshire vs friscv axi vs nmigen cheshire vs pulpissimo axi vs fusesoc cheshire vs rp32 axi vs opentitan cheshire vs libsv axi vs qemu cheshire vs cva6 axi vs Pyverilog