hdlConvertor
edalize
hdlConvertor | edalize | |
---|---|---|
1 | 4 | |
266 | 593 | |
- | - | |
5.8 | 7.2 | |
3 months ago | 7 days ago | |
C++ | Python | |
MIT License | BSD 2-clause "Simplified" License |
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hdlConvertor
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VHDL backend
Have you seen https://github.com/dalance/sv-parser, https://github.com/google/verible, https://github.com/alainmarcel/Surelog, https://github.com/Nic30/hdlConvertor? I think there was at least one more that I stumbled across, but can't find at the moment.
edalize
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Dropping EDA-GUI's 101
Check out FuseSoC: https://github.com/olofk/fusesoc which can handle Vivado builds for you (utilizing edalize: https://github.com/olofk/edalize) along with some nice package management. It can run against multiple tools so you can also get it to build simulations using Verilator or a commercial EDA tool if you have access to them.
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Introduction to FPGAs
Check out https://github.com/olofk/fusesoc. It gives you a command line build flow that can drive Vivado (along with many other eda tools via edalize https://github.com/olofk/edalize) without having to touch the GUI (though you might want it for programming the board, though FuseSoC can do that too).
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Compiling Code into Silicon
This reminds me very much of edalize[1], which does something very similar.
[1]: https://github.com/olofk/edalize
- Olof Kindgren on LinkedIn: We have a new world record! 6000 RISC-V cores in a single chip!
What are some alternatives?
circt - Circuit IR Compilers and Tools
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
vscode-terosHDL - VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
naja-verilog - A standalone structural (gate-level) verilog parser
freepdk-45nm - ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
rggen - Code generation tool for control and status registers
apio - :seedling: Open source ecosystem for open FPGA boards
Surelog - SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
icestudio - :snowflake: Visual editor for open FPGA boards
verible - Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server