hdlConvertor
rggen
hdlConvertor | rggen | |
---|---|---|
1 | 3 | |
266 | 279 | |
- | 1.8% | |
5.8 | 7.7 | |
3 months ago | 3 months ago | |
C++ | Ruby | |
MIT License | MIT License |
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hdlConvertor
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VHDL backend
Have you seen https://github.com/dalance/sv-parser, https://github.com/google/verible, https://github.com/alainmarcel/Surelog, https://github.com/Nic30/hdlConvertor? I think there was at least one more that I stumbled across, but can't find at the moment.
rggen
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RgGen v0.28.0
I've released RgGen v0.28.0! https://github.com/rggen/rggen/releases/tag/v0.28.0 This release includes following updates.
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RgGen update (support C header file generation)
RgGen is a code generation tool for configuration and status registers. RgGen can generate SV/Verilog/VHDL RTL, UVM RAL model and Markdown documents from readable register map specifications. https://github.com/rggen/rggen
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RgGen update
I just released the latest RgGen v0.26.0! https://github.com/rggen/rggen/releases/tag/v0.26.0
What are some alternatives?
circt - Circuit IR Compilers and Tools
PeakRDL-uvm - Generate UVM register model from compiled SystemRDL input
vscode-terosHDL - VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
open-register-design-tool - Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
naja-verilog - A standalone structural (gate-level) verilog parser
PeakRDL-ipxact - Import and export IP-XACT XML register models
Surelog - SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
edalize - An abstraction library for interfacing EDA tools
verible - Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
clash-ghc - Haskell to VHDL/Verilog/SystemVerilog compiler
rggen-sv-rtl - Common SystemVerilog RTL modules for RgGen