rggen VS PeakRDL-uvm

Compare rggen vs PeakRDL-uvm and see what are their differences.

rggen

Code generation tool for control and status registers (by rggen)
Verilog Systemverilog Uvm Rtl Ral Csr soc Fpga Asic register-descriptions uvm-ral-model wiki-documents amba axi apb uvm-register-model eda Vhdl wishbone-bus
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PeakRDL-uvm

Generate UVM register model from compiled SystemRDL input (by SystemRDL)
uvm-register-model uvm-ral-model Asic Fpga Uvm eda registers
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rggen PeakRDL-uvm
3 1
277 45
4.3% -
7.7 5.5
3 months ago 3 months ago
Ruby Python
MIT License GNU General Public License v3.0 only
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

rggen

Posts with mentions or reviews of rggen. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-06-13.
  • RgGen v0.28.0
    1 project | /r/u_taichi730 | 11 Oct 2022
    I've released RgGen v0.28.0! https://github.com/rggen/rggen/releases/tag/v0.28.0 This release includes following updates.
  • RgGen update (support C header file generation)
    3 projects | /r/u_taichi730 | 13 Jun 2022
    RgGen is a code generation tool for configuration and status registers. RgGen can generate SV/Verilog/VHDL RTL, UVM RAL model and Markdown documents from readable register map specifications. https://github.com/rggen/rggen
  • RgGen update
    4 projects | /r/FPGA | 25 Mar 2022
    I just released the latest RgGen v0.26.0! https://github.com/rggen/rggen/releases/tag/v0.26.0

PeakRDL-uvm

Posts with mentions or reviews of PeakRDL-uvm. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-03-20.
  • PeakRDL-Regblock: A free & open source tool that generates SystemVerilog control & status registers (CSR) from SystemRDL
    3 projects | /r/FPGA | 20 Mar 2022
    If you're interested register automation, be sure to check out some of my other projects: * systemrdl-compiler * Compiler front-end for the SystemRDL 2.0 language. Want to generate something yourself from SystemRDL input? No problem - use this language interpreter as your front-end. * PeakRDL-html * Generates dynamic and pretty looking HTML documentation * PeakRDL-ipxact * Import/export IP-XACT XML * PeakRDL-uvm * Generate a UVM register model * And a bunch of other random stuff under my SystemRDL GitHub project.

What are some alternatives?

When comparing rggen and PeakRDL-uvm you can also consider the following projects:

open-register-design-tool - Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

PeakRDL-ipxact - Import and export IP-XACT XML register models

PeakRDL-html - Generate address space documentation HTML from compiled SystemRDL input

edalize - An abstraction library for interfacing EDA tools

pygears - HW Design: A Functional Approach

vscode-terosHDL - VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

rggen-sv-rtl - Common SystemVerilog RTL modules for RgGen

hdlConvertor - Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

gf180mcu-pdk - PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).

veryl - Veryl: A Modern Hardware Description Language

systemrdl-compiler - SystemRDL 2.0 language compiler front-end

rggen vs open-register-design-tool PeakRDL-uvm vs skywater-pdk rggen vs PeakRDL-ipxact PeakRDL-uvm vs PeakRDL-html rggen vs edalize PeakRDL-uvm vs pygears rggen vs vscode-terosHDL rggen vs rggen-sv-rtl rggen vs hdlConvertor rggen vs gf180mcu-pdk rggen vs veryl rggen vs systemrdl-compiler