hdlConvertor
verible
| hdlConvertor | verible | |
|---|---|---|
| 1 | 6 | |
| 266 | 1,189 | |
| - | 1.2% | |
| 5.8 | 9.3 | |
| 3 months ago | 8 days ago | |
| C++ | C++ | |
| MIT License | GNU General Public License v3.0 or later |
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hdlConvertor
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VHDL backend
Have you seen https://github.com/dalance/sv-parser, https://github.com/google/verible, https://github.com/alainmarcel/Surelog, https://github.com/Nic30/hdlConvertor? I think there was at least one more that I stumbled across, but can't find at the moment.
verible
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How to instance module with auto-completion for verilog in neovim?
I want to write Verilog/SystemVerilog with neovim(I use Lazyvim,nvim-lspconfig,mason.nvim, mason-lspconfig.nvim and nvim-cmp) . Now I use Verible to format and lint. But it seems that it cannot complete the signals when I want to instance a module and type a "." . So is there a better way to interconnect modules?
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Verilog LRM syntax rules
BTW, I'd recommend checking out verible if you're looking for a flex/bison verilog parser.
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Reliable Verilog dependency analysis
You'll have to roll up your sleeves a bit, but Verible might be worth a look for a functional SystemVerilog parser that you could build off of. It's the only thing I'm aware of built for this class of tools (e.g. yosys is only synthesizable verilog) that's available and likely to cover a good amount of the spec.
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svls VS verible - a user suggested alternative
2 projects | 3 Nov 2021
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Tools like Scitools Understand but support Verilog
https://github.com/chipsalliance/verible (may not do actual syntax checking)
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Forking rustfmt for another language
You might be interested in this though.
What are some alternatives?
circt - Circuit IR Compilers and Tools
slang - SystemVerilog compiler and language services
vscode-terosHDL - VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
svls - SystemVerilog language server
naja-verilog - A standalone structural (gate-level) verilog parser
Surelog - SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
rggen - Code generation tool for control and status registers
veridian - A SystemVerilog Language Server
Surelog - SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
clash-ghc - Haskell to VHDL/Verilog/SystemVerilog compiler
tree-sitter-html - HTML grammar for Tree-sitter