hdlConvertor VS naja-verilog

Compare hdlConvertor vs naja-verilog and see what are their differences.

hdlConvertor

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4 (by Nic30)
Parser Verilog Fpga Vhdl Systemverilog systemverilog-parser vhdl-parser verilog-parser antrl4 Python
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naja-verilog

A standalone structural (gate-level) verilog parser (by najaeda)
CPP eda netlist netlist-parser semiconductor Verilog electronic-design-automation Parser
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hdlConvertor naja-verilog
1 2
266 21
- -
5.8 7.6
3 months ago 30 days ago
C++ C++
MIT License Apache License 2.0
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
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For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

hdlConvertor

Posts with mentions or reviews of hdlConvertor. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-01-24.
  • VHDL backend
    2 projects | /r/FPGA | 24 Jan 2021
    Have you seen https://github.com/dalance/sv-parser, https://github.com/google/verible, https://github.com/alainmarcel/Surelog, https://github.com/Nic30/hdlConvertor? I think there was at least one more that I stumbled across, but can't find at the moment.

naja-verilog

Posts with mentions or reviews of naja-verilog. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-10-11.
  • Naja-Verilog: stand-alone structural (gate-level) parser
    2 projects | /r/FPGA | 11 Oct 2023
    Hi everyone, If you need to build C++ (or Python) application loading gate level verilog, similar to the one at the input of FPGA PnR tools, https://github.com/xtofalex/naja-verilog is available. This parser has been designed to allow the construction on the fly of any netlist data structure. One note: if you need also a C++ netlist data structure (with Python bindings) to build netlist analysis or editing tools on top, Naja SNL: https://github.com/xtofalex/naja is also ready for use. Hope this is useful. If it is or if you face any issue, please reach to me. Feedback welcome.
  • Show HN: Naja-Verilog – Structural Verilog Parser
    2 projects | news.ycombinator.com | 24 Mar 2023

What are some alternatives?

When comparing hdlConvertor and naja-verilog you can also consider the following projects:

circt - Circuit IR Compilers and Tools

Degate - A modern and open-source cross-platform software for chips reverse engineering.

vscode-terosHDL - VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

verilator - Verilator open-source SystemVerilog simulator and lint system

rggen - Code generation tool for control and status registers

Surelog - SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

naja - Structural Netlist API (and more) for EDA post synthesis flow development

verible - Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

spydrnet - A flexible framework for analyzing and transforming FPGA netlists. Official repository.

clash-ghc - Haskell to VHDL/Verilog/SystemVerilog compiler

edalize - An abstraction library for interfacing EDA tools

hdlConvertor vs circt naja-verilog vs Degate hdlConvertor vs vscode-terosHDL naja-verilog vs verilator hdlConvertor vs rggen naja-verilog vs Surelog hdlConvertor vs Surelog naja-verilog vs naja hdlConvertor vs verible naja-verilog vs spydrnet hdlConvertor vs clash-ghc hdlConvertor vs edalize