Naja-verilog Alternatives
Similar projects and alternatives to naja-verilog based on common topics and language
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InfluxDB
Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.
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hdlConvertor
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
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Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX (by chipsalliance)
NOTE:
The number of mentions on this list indicates mentions on common posts plus user suggested alternatives.
Hence, a higher number means a better naja-verilog alternative or higher similarity.
naja-verilog reviews and mentions
Posts with mentions or reviews of naja-verilog.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-10-11.
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Naja-Verilog: stand-alone structural (gate-level) parser
Hi everyone, If you need to build C++ (or Python) application loading gate level verilog, similar to the one at the input of FPGA PnR tools, https://github.com/xtofalex/naja-verilog is available. This parser has been designed to allow the construction on the fly of any netlist data structure. One note: if you need also a C++ netlist data structure (with Python bindings) to build netlist analysis or editing tools on top, Naja SNL: https://github.com/xtofalex/naja is also ready for use. Hope this is useful. If it is or if you face any issue, please reach to me. Feedback welcome.
- Show HN: Naja-Verilog – Structural Verilog Parser
Stats
Basic naja-verilog repo stats
2
21
7.6
26 days ago
najaeda/naja-verilog is an open source project licensed under Apache License 2.0 which is an OSI approved license.
The primary programming language of naja-verilog is C++.
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