rggen VS edalize

Compare rggen vs edalize and see what are their differences.

rggen

Code generation tool for control and status registers (by rggen)
Verilog Systemverilog Uvm Rtl Ral Csr soc Fpga Asic register-descriptions uvm-ral-model wiki-documents amba axi apb uvm-register-model eda Vhdl wishbone-bus
Source Code
Suggest alternative
Edit details

edalize

An abstraction library for interfacing EDA tools (by olofk)
eda Fpga fossi Xilinx altera lattice yosys Synthesis Simulation Verilog Vhdl Systemverilog Verilator icarus-verilog modelsim riviera-pro ghdl icestorm spyglass vivado
Source Code
Suggest alternative
Edit details
WorkOS
Our great sponsors
  • WorkOS - The modern identity platform for B2B SaaS
  • InfluxDB - Power Real-Time Data Analytics at Scale
  • SaaSHub - Software Alternatives and Reviews
Our great sponsors
rggen edalize
3 4
277 590
4.3% -
7.7 7.3
3 months ago 9 days ago
Ruby Python
MIT License BSD 2-clause "Simplified" License
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

rggen

Posts with mentions or reviews of rggen. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-06-13.
  • RgGen v0.28.0
    1 project | /r/u_taichi730 | 11 Oct 2022
    I've released RgGen v0.28.0! https://github.com/rggen/rggen/releases/tag/v0.28.0 This release includes following updates.
  • RgGen update (support C header file generation)
    3 projects | /r/u_taichi730 | 13 Jun 2022
    RgGen is a code generation tool for configuration and status registers. RgGen can generate SV/Verilog/VHDL RTL, UVM RAL model and Markdown documents from readable register map specifications. https://github.com/rggen/rggen
  • RgGen update
    4 projects | /r/FPGA | 25 Mar 2022
    I just released the latest RgGen v0.26.0! https://github.com/rggen/rggen/releases/tag/v0.26.0

edalize

Posts with mentions or reviews of edalize. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-02-06.
  • Dropping EDA-GUI's 101
    1 project | /r/FPGA | 17 Feb 2023
    Check out FuseSoC: https://github.com/olofk/fusesoc which can handle Vivado builds for you (utilizing edalize: https://github.com/olofk/edalize) along with some nice package management. It can run against multiple tools so you can also get it to build simulations using Verilator or a commercial EDA tool if you have access to them.
  • Introduction to FPGAs
    9 projects | news.ycombinator.com | 6 Feb 2023
    Check out https://github.com/olofk/fusesoc. It gives you a command line build flow that can drive Vivado (along with many other eda tools via edalize https://github.com/olofk/edalize) without having to touch the GUI (though you might want it for programming the board, though FuseSoC can do that too).
  • Compiling Code into Silicon
    10 projects | news.ycombinator.com | 7 Dec 2021
    This reminds me very much of edalize[1], which does something very similar.

    [1]: https://github.com/olofk/edalize

  • Olof Kindgren on LinkedIn: We have a new world record! 6000 RISC-V cores in a single chip!
    3 projects | /r/RISCV | 24 Sep 2021

What are some alternatives?

When comparing rggen and edalize you can also consider the following projects:

PeakRDL-uvm - Generate UVM register model from compiled SystemRDL input

fusesoc - Package manager and build abstraction tool for FPGA/ASIC development

open-register-design-tool - Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

PeakRDL-ipxact - Import and export IP-XACT XML register models

freepdk-45nm - ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen

vscode-terosHDL - VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

apio - :seedling: Open source ecosystem for open FPGA boards

rggen-sv-rtl - Common SystemVerilog RTL modules for RgGen

icestudio - :snowflake: Visual editor for open FPGA boards

hdlConvertor - Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

sphinx-vhdl

rggen vs PeakRDL-uvm edalize vs fusesoc rggen vs open-register-design-tool edalize vs skywater-pdk rggen vs PeakRDL-ipxact edalize vs freepdk-45nm rggen vs vscode-terosHDL edalize vs apio rggen vs rggen-sv-rtl edalize vs icestudio rggen vs hdlConvertor edalize vs sphinx-vhdl