rggen VS hdlConvertor

Compare rggen vs hdlConvertor and see what are their differences.

rggen

Code generation tool for control and status registers (by rggen)
Verilog Systemverilog Uvm Rtl Ral Csr soc Fpga Asic register-descriptions uvm-ral-model wiki-documents amba axi apb uvm-register-model eda Vhdl wishbone-bus
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hdlConvertor

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4 (by Nic30)
Parser Verilog Fpga Vhdl Systemverilog systemverilog-parser vhdl-parser verilog-parser antrl4 Python
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rggen hdlConvertor
3 1
279 266
1.8% -
7.7 5.8
3 months ago 3 months ago
Ruby C++
MIT License MIT License
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

rggen

Posts with mentions or reviews of rggen. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-06-13.
  • RgGen v0.28.0
    1 project | /r/u_taichi730 | 11 Oct 2022
    I've released RgGen v0.28.0! https://github.com/rggen/rggen/releases/tag/v0.28.0 This release includes following updates.
  • RgGen update (support C header file generation)
    3 projects | /r/u_taichi730 | 13 Jun 2022
    RgGen is a code generation tool for configuration and status registers. RgGen can generate SV/Verilog/VHDL RTL, UVM RAL model and Markdown documents from readable register map specifications. https://github.com/rggen/rggen
  • RgGen update
    4 projects | /r/FPGA | 25 Mar 2022
    I just released the latest RgGen v0.26.0! https://github.com/rggen/rggen/releases/tag/v0.26.0

hdlConvertor

Posts with mentions or reviews of hdlConvertor. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-01-24.
  • VHDL backend
    2 projects | /r/FPGA | 24 Jan 2021
    Have you seen https://github.com/dalance/sv-parser, https://github.com/google/verible, https://github.com/alainmarcel/Surelog, https://github.com/Nic30/hdlConvertor? I think there was at least one more that I stumbled across, but can't find at the moment.

What are some alternatives?

When comparing rggen and hdlConvertor you can also consider the following projects:

PeakRDL-uvm - Generate UVM register model from compiled SystemRDL input

circt - Circuit IR Compilers and Tools

open-register-design-tool - Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

vscode-terosHDL - VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

PeakRDL-ipxact - Import and export IP-XACT XML register models

naja-verilog - A standalone structural (gate-level) verilog parser

edalize - An abstraction library for interfacing EDA tools

Surelog - SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

verible - Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

rggen-sv-rtl - Common SystemVerilog RTL modules for RgGen

clash-ghc - Haskell to VHDL/Verilog/SystemVerilog compiler

rggen vs PeakRDL-uvm hdlConvertor vs circt rggen vs open-register-design-tool hdlConvertor vs vscode-terosHDL rggen vs PeakRDL-ipxact hdlConvertor vs naja-verilog rggen vs edalize hdlConvertor vs Surelog rggen vs vscode-terosHDL hdlConvertor vs verible rggen vs rggen-sv-rtl hdlConvertor vs clash-ghc