rggen VS rggen-sv-rtl

Compare rggen vs rggen-sv-rtl and see what are their differences.

rggen

Code generation tool for control and status registers (by rggen)
Verilog Systemverilog Uvm Rtl Ral Csr soc Fpga Asic register-descriptions uvm-ral-model wiki-documents amba axi apb uvm-register-model eda Vhdl wishbone-bus
Source Code
Suggest alternative
Edit details

rggen-sv-rtl

Common SystemVerilog RTL modules for RgGen (by rggen)
Systemverilog Rtl apb Axi4 axi
Source Code
github.com
Suggest alternative
Edit details
InfluxDB
Our great sponsors
  • InfluxDB - Power Real-Time Data Analytics at Scale
  • WorkOS - The modern identity platform for B2B SaaS
  • SaaSHub - Software Alternatives and Reviews
Our great sponsors
rggen rggen-sv-rtl
3 1
277 10
4.3% -
7.7 4.7
2 months ago 3 months ago
Ruby SystemVerilog
MIT License MIT License
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

rggen

Posts with mentions or reviews of rggen. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-06-13.
  • RgGen v0.28.0
    1 project | /r/u_taichi730 | 11 Oct 2022
    I've released RgGen v0.28.0! https://github.com/rggen/rggen/releases/tag/v0.28.0 This release includes following updates.
  • RgGen update (support C header file generation)
    3 projects | /r/u_taichi730 | 13 Jun 2022
    RgGen is a code generation tool for configuration and status registers. RgGen can generate SV/Verilog/VHDL RTL, UVM RAL model and Markdown documents from readable register map specifications. https://github.com/rggen/rggen
  • RgGen update
    4 projects | /r/FPGA | 25 Mar 2022
    I just released the latest RgGen v0.26.0! https://github.com/rggen/rggen/releases/tag/v0.26.0

rggen-sv-rtl

Posts with mentions or reviews of rggen-sv-rtl. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-03-25.

What are some alternatives?

When comparing rggen and rggen-sv-rtl you can also consider the following projects:

PeakRDL-uvm - Generate UVM register model from compiled SystemRDL input

Cores-VeeR-EL2 - VeeR EL2 Core

open-register-design-tool - Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Cores-VeeR-EH1 - VeeR EH1 core

PeakRDL-ipxact - Import and export IP-XACT XML register models

rggen-vhdl-rtl

edalize - An abstraction library for interfacing EDA tools

rggen-verilog-rtl - Common Verilog RTL modules for RgGen

vscode-terosHDL - VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

hdlConvertor - Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

gf180mcu-pdk - PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).

veryl - Veryl: A Modern Hardware Description Language

rggen vs PeakRDL-uvm rggen-sv-rtl vs Cores-VeeR-EL2 rggen vs open-register-design-tool rggen-sv-rtl vs Cores-VeeR-EH1 rggen vs PeakRDL-ipxact rggen-sv-rtl vs rggen-vhdl-rtl rggen vs edalize rggen-sv-rtl vs rggen-verilog-rtl rggen vs vscode-terosHDL rggen vs hdlConvertor rggen vs gf180mcu-pdk rggen vs veryl