TCB VS axi

Compare TCB vs axi and see what are their differences.

TCB

Tightly Coupled Bus, low complexity, high performance system bus. (by jeras)
system-bus Systemverilog
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axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication (by pulp-platform)
axi Axi4 axi4-lite Systemverilog Hardware network-on-chip Asic Fpga Rtl IP
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TCB axi
1 3
1 933
- 3.3%
8.2 6.1
7 months ago 6 days ago
SystemVerilog SystemVerilog
Apache License 2.0 GNU General Public License v3.0 or later
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

TCB

Posts with mentions or reviews of TCB. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-01-10.
  • Simple skid buffer implementation
    3 projects | /r/FPGA | 10 Jan 2023
    I am working on a simple system bus specification TCB, so I spent some time reading your article. I hope to write the required formal rules someday, but a full input/output/state transition table would also be useful for readers. The implementation correctness can be shown by arguing all rows in a logic table provide the correct behavior. This is not very useful for verification automation, but can be easier to understand for readers with basic logic design education.

axi

Posts with mentions or reviews of axi. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-06-28.

What are some alternatives?

When comparing TCB and axi you can also consider the following projects:

wb2axip - Bus bridges and other odds and ends

chisel - Chisel: A Modern Hardware Design Language

nmigen - A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen

fusesoc - Package manager and build abstraction tool for FPGA/ASIC development

opentitan - OpenTitan: Open source silicon root of trust

qemu - Xilinx's fork of Quick EMUlator (QEMU) with improved support and modelling for the Xilinx platforms.

Pyverilog - Python-based Hardware Design Processing Toolkit for Verilog HDL

Cores-VeeR-EL2 - VeeR EL2 Core

tiny-cores - Collection of assorted small cores

myhdl - The MyHDL development repository

basejump_stl - BaseJump STL: A Standard Template Library for SystemVerilog

open-register-design-tool - Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

TCB vs wb2axip axi vs chisel axi vs nmigen axi vs fusesoc axi vs opentitan axi vs qemu axi vs Pyverilog axi vs Cores-VeeR-EL2 axi vs tiny-cores axi vs myhdl axi vs basejump_stl axi vs open-register-design-tool