TCB Alternatives

Similar projects and alternatives to TCB based on common topics and language

wb2axip

51 433 3.1 Verilog TCB VS wb2axip

Bus bridges and other odds and ends
SpinalHDL

8 1,518 9.8 Scala TCB VS SpinalHDL

Scala based HDL
WorkOS

workos.com sponsored

The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.
hdmi

7 1,008 4.7 SystemVerilog TCB VS hdmi

Send video/audio over HDMI on an FPGA
axi

3 922 6.8 SystemVerilog TCB VS axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
cheshire

1 102 7.8 SystemVerilog TCB VS cheshire

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6 (by pulp-platform)
BrianHG-DDR3-Controller

2 60 10.0 SystemVerilog TCB VS BrianHG-DDR3-Controller

DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
libsv

2 19 3.6 SystemVerilog TCB VS libsv

An open source, parameterized SystemVerilog digital hardware IP library
InfluxDB

www.influxdata.com sponsored

Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better TCB alternative or higher similarity.

Suggest an alternative to TCB

TCB reviews and mentions

Posts with mentions or reviews of TCB. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-01-10.

Simple skid buffer implementation
3 projects | /r/FPGA | 10 Jan 2023

I am working on a simple system bus specification TCB, so I spent some time reading your article. I hope to write the required formal rules someday, but a full input/output/state transition table would also be useful for readers. The implementation correctness can be shown by arguing all rows in a logic table provide the correct behavior. This is not very useful for verification automation, but can be easier to understand for readers with basic logic design education.