Tightly Coupled Bus, low complexity, high performance system bus. (by jeras)

TCB Alternatives

Similar projects and alternatives to TCB based on common topics and language

  • wb2axip

    1 TCB VS wb2axip

    Bus bridges and other odds and ends

  • SpinalHDL

    1 TCB VS SpinalHDL

    Scala based HDL

  • Onboard AI

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  • hdmi

    0 TCB VS hdmi

    Send video/audio over HDMI on an FPGA

  • axi

    0 TCB VS axi

    AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

  • cheshire

    0 TCB VS cheshire

    A minimal Linux-capable 64-bit RISC-V SoC built around CVA6 (by pulp-platform)

  • BrianHG-DDR3-Controller

    DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

  • libsv

    0 TCB VS libsv

    An open source, parameterized SystemVerilog digital hardware IP library

  • InfluxDB

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NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better TCB alternative or higher similarity.

TCB reviews and mentions

Posts with mentions or reviews of TCB. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-01-10.
  • Simple skid buffer implementation
    3 projects | /r/FPGA | 10 Jan 2023
    I am working on a simple system bus specification TCB, so I spent some time reading your article. I hope to write the required formal rules someday, but a full input/output/state transition table would also be useful for readers. The implementation correctness can be shown by arguing all rows in a logic table provide the correct behavior. This is not very useful for verification automation, but can be easier to understand for readers with basic logic design education.


Basic TCB repo stats
about 2 months ago

jeras/TCB is an open source project licensed under Apache License 2.0 which is an OSI approved license.

The primary programming language of TCB is SystemVerilog.

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