TCB
Tightly Coupled Bus, low complexity, high performance system bus. (by jeras)
BrianHG-DDR3-Controller
DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included. (by BrianHGinc)
| TCB | BrianHG-DDR3-Controller | |
|---|---|---|
| 1 | 2 | |
| 1 | 60 | |
| - | - | |
| 8.2 | 10.0 | |
| 7 months ago | almost 2 years ago | |
| SystemVerilog | SystemVerilog | |
| Apache License 2.0 | - |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
TCB
Posts with mentions or reviews of TCB.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-01-10.
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Simple skid buffer implementation
I am working on a simple system bus specification TCB, so I spent some time reading your article. I hope to write the required formal rules someday, but a full input/output/state transition table would also be useful for readers. The implementation correctness can be shown by arguing all rows in a logic table provide the correct behavior. This is not very useful for verification automation, but can be easier to understand for readers with basic logic design education.
BrianHG-DDR3-Controller
Posts with mentions or reviews of BrianHG-DDR3-Controller.
We have used some of these posts to build our list of alternatives
and similar projects.
- Is there a completely free computer?
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Open source Verilog functional simulation library for a PSRAM / HyperRAM controller?
I’ll point you here. Intel give away a stand-alone version of Modelsim, which can be run without a license file in a reduced capability mode that’s been fine for anything I’ve thrown at it - recently for example the DDR3 controller from BrianHG, which has a reasonably extensive verification setup.
What are some alternatives?
When comparing TCB and BrianHG-DDR3-Controller you can also consider the following projects:
wb2axip - Bus bridges and other odds and ends
fpga-docker - Tools for running FPGA vendor toolchains with Docker
ulm-on-ice - ULM (Ulm Lecture Machine) on ice40
ApogeoRV - A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.