TCB
hdmi
| TCB | hdmi | |
|---|---|---|
| 1 | 7 | |
| 1 | 1,021 | |
| - | 2.5% | |
| 8.2 | 4.7 | |
| 7 months ago | 3 months ago | |
| SystemVerilog | SystemVerilog | |
| Apache License 2.0 | GNU General Public License v3.0 or later |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
TCB
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Simple skid buffer implementation
I am working on a simple system bus specification TCB, so I spent some time reading your article. I hope to write the required formal rules someday, but a full input/output/state transition table would also be useful for readers. The implementation correctness can be shown by arguing all rows in a logic table provide the correct behavior. This is not very useful for verification automation, but can be easier to understand for readers with basic logic design education.
hdmi
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HDMI Forum Rejects Open-Source HDMI 2.1 Driver Support Sought by AMD
Relevant caveat from its readme: https://github.com/hdl-util/hdmi?tab=readme-ov-file#hdmi-ado...
- I want to learn to interface HDMI to Xilinx Kintex 7 FPGA. Can you please provide any resources? I don't have prior experience in interfacing HDMI.
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HDMI Output Pynq Z2 PL
If you want real HDMI you can use https://github.com/hdl-util/hdmi
- Any good guides for learning how HDMI and DP function at a low level?
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HDMI not showing up in IP Core Generator
Yep, thanks :) - I found Sameer’s github repository soon after posting (of course). His repo got some Gowin-specific code a couple of months ago. It didn’t synthesize straight away - the serializer code was ignoring the `if GW_IDE directive and trying to synthesize the Altera code, but stripping that file down to the Gowin-only part made it synthesize ok.
What are some alternatives?
wb2axip - Bus bridges and other odds and ends
nestang - NESTang is an FPGA Nintendo Entertainment System implemented with Sipeed Tang Primer 25K, Nano 20K and Primer 20K boards
eurorack-pmod - A eurorack-friendly audio frontend compatible with many FPGA boards.
cheshire - A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
icebreaker-verilog-examples - This repository contains small example designs that can be used with the open source icestorm flow.
YuzukiLOHCC-PRO - Low cost USB3.2Gen1 HDMI-USB Video Acquisition With Loop Out (Loop Out HDMI Capture Card) base on MS2130 & MS9332
openfpga-NES - NES for the Analogue Pocket
analogue-pocket-utils - Collection of IP and information on how to develop for openFPGA and Analogue Pocket
netv2-fpga-dvi-decoder - HDMI/DVI decoder for NeTV2 FPGA
PYNQ - Python Productivity for ZYNQ
fpga-docker - Tools for running FPGA vendor toolchains with Docker