hdmi
cheshire
| hdmi | cheshire | |
|---|---|---|
| 7 | 1 | |
| 1,021 | 128 | |
| 2.5% | 25.0% | |
| 4.7 | 7.6 | |
| 3 months ago | 4 days ago | |
| SystemVerilog | SystemVerilog | |
| GNU General Public License v3.0 or later | GNU General Public License v3.0 or later |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
hdmi
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HDMI Forum Rejects Open-Source HDMI 2.1 Driver Support Sought by AMD
Relevant caveat from its readme: https://github.com/hdl-util/hdmi?tab=readme-ov-file#hdmi-ado...
- I want to learn to interface HDMI to Xilinx Kintex 7 FPGA. Can you please provide any resources? I don't have prior experience in interfacing HDMI.
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HDMI Output Pynq Z2 PL
If you want real HDMI you can use https://github.com/hdl-util/hdmi
- Any good guides for learning how HDMI and DP function at a low level?
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HDMI not showing up in IP Core Generator
Yep, thanks :) - I found Sameer’s github repository soon after posting (of course). His repo got some Gowin-specific code a couple of months ago. It didn’t synthesize straight away - the serializer code was ignoring the `if GW_IDE directive and trying to synthesize the Altera code, but stripping that file down to the Gowin-only part made it synthesize ok.
cheshire
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Cpu project
If you want to see the difference in scale you may want to compare the Cheshire SoC (Linux capable) here
What are some alternatives?
nestang - NESTang is an FPGA Nintendo Entertainment System implemented with Sipeed Tang Primer 25K, Nano 20K and Primer 20K boards
friscv - RISCV CPU implementation in SystemVerilog
eurorack-pmod - A eurorack-friendly audio frontend compatible with many FPGA boards.
pulpissimo - This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
icebreaker-verilog-examples - This repository contains small example designs that can be used with the open source icestorm flow.
rp32 - RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
YuzukiLOHCC-PRO - Low cost USB3.2Gen1 HDMI-USB Video Acquisition With Loop Out (Loop Out HDMI Capture Card) base on MS2130 & MS9332
libsv - An open source, parameterized SystemVerilog digital hardware IP library
openfpga-NES - NES for the Analogue Pocket
axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
analogue-pocket-utils - Collection of IP and information on how to develop for openFPGA and Analogue Pocket
cva6 - The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux