hdmi
Send video/audio over HDMI on an FPGA (by hdl-util)
icebreaker-verilog-examples
This repository contains small example designs that can be used with the open source icestorm flow. (by icebreaker-fpga)
| hdmi | icebreaker-verilog-examples | |
|---|---|---|
| 7 | 1 | |
| 1,024 | 133 | |
| 2.8% | 3.0% | |
| 4.7 | 10.0 | |
| 4 months ago | over 2 years ago | |
| SystemVerilog | Verilog | |
| GNU General Public License v3.0 or later | - |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
hdmi
Posts with mentions or reviews of hdmi.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2024-02-28.
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HDMI Forum Rejects Open-Source HDMI 2.1 Driver Support Sought by AMD
Relevant caveat from its readme: https://github.com/hdl-util/hdmi?tab=readme-ov-file#hdmi-ado...
- I want to learn to interface HDMI to Xilinx Kintex 7 FPGA. Can you please provide any resources? I don't have prior experience in interfacing HDMI.
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HDMI Output Pynq Z2 PL
If you want real HDMI you can use https://github.com/hdl-util/hdmi
- Any good guides for learning how HDMI and DP function at a low level?
-
HDMI not showing up in IP Core Generator
Yep, thanks :) - I found Sameer’s github repository soon after posting (of course). His repo got some Gowin-specific code a couple of months ago. It didn’t synthesize straight away - the serializer code was ignoring the `if GW_IDE directive and trying to synthesize the Altera code, but stripping that file down to the Gowin-only part made it synthesize ok.
icebreaker-verilog-examples
Posts with mentions or reviews of icebreaker-verilog-examples.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-12-31.
-
HDMI Output Pynq Z2 PL
You want to use the DVI protocol over HDMI. You will need your frame data either from a simple state machine or using Xilinx VDMA IP to load it from DDR. Then you need to convert that data into HSYNC and VSYNC data, here are two examples, AXI4-Stream to Video or IceBreaker HDL example. You then need to use IOserdes blocks to convert it to the HDMI TDMS signals (rgb2dvi core). You can follow the block diagram for the Pynq Z2 FPGA on the Pynq github (bd tcl).
What are some alternatives?
When comparing hdmi and icebreaker-verilog-examples you can also consider the following projects:
nestang - NESTang is an FPGA Nintendo Entertainment System implemented with Sipeed Tang Primer 25K, Nano 20K and Primer 20K boards
PYNQ - Python Productivity for ZYNQ
eurorack-pmod - A eurorack-friendly audio frontend compatible with many FPGA boards.
cheshire - A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
YuzukiLOHCC-PRO - Low cost USB3.2Gen1 HDMI-USB Video Acquisition With Loop Out (Loop Out HDMI Capture Card) base on MS2130 & MS9332
openfpga-NES - NES for the Analogue Pocket
analogue-pocket-utils - Collection of IP and information on how to develop for openFPGA and Analogue Pocket
netv2-fpga-dvi-decoder - HDMI/DVI decoder for NeTV2 FPGA
fpga-docker - Tools for running FPGA vendor toolchains with Docker