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HDMI Output Pynq Z2 PL
4 projects | /r/FPGA | 31 Dec 2022

You want to use the DVI protocol over HDMI. You will need your frame data either from a simple state machine or using Xilinx VDMA IP to load it from DDR. Then you need to convert that data into HSYNC and VSYNC data, here are two examples, AXI4-Stream to Video or IceBreaker HDL example. You then need to use IOserdes blocks to convert it to the HDMI TDMS signals (rgb2dvi core). You can follow the block diagram for the Pynq Z2 FPGA on the Pynq github (bd tcl).

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Basic icebreaker-verilog-examples repo stats

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133

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10.0

Last Commit

over 2 years ago

The primary programming language of icebreaker-verilog-examples is Verilog.

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