simple10GbaseR
axi
| simple10GbaseR | axi | |
|---|---|---|
| 1 | 3 | |
| 4 | 930 | |
| - | 3.0% | |
| 0.0 | 6.1 | |
| almost 2 years ago | 3 days ago | |
| SystemVerilog | SystemVerilog | |
| MIT License | GNU General Public License v3.0 or later |
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simple10GbaseR
axi
- AXI InterConnect
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Any recommendations for an RTL "standard library"?
Hi, I’m one of the developers of basejump. It’s pretty awesome, especially if you’re targeting ASIC. Nearly all the components have been through multiple advanced node tapeouts. The only weakness I see is a lack of AXI components. So I may suggest https://github.com/pulp-platform/axi to supplement
- How to compare HDL simulation/implementation results to Matlab?
What are some alternatives?
chisel - Chisel: A Modern Hardware Design Language
nmigen - A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
opentitan - OpenTitan: Open source silicon root of trust
qemu - Xilinx's fork of Quick EMUlator (QEMU) with improved support and modelling for the Xilinx platforms.
Pyverilog - Python-based Hardware Design Processing Toolkit for Verilog HDL
Cores-VeeR-EL2 - VeeR EL2 Core
tiny-cores - Collection of assorted small cores
myhdl - The MyHDL development repository
basejump_stl - BaseJump STL: A Standard Template Library for SystemVerilog
open-register-design-tool - Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
surf - A huge VHDL library for FPGA development