SystemVerilog Ethernet

Open-source SystemVerilog projects categorized as Ethernet

Topics: Fpga 10gbase-r

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SystemVerilog Ethernet Projects

simple10GbaseR

1 4 0.0 SystemVerilog

FPGA low latency 10GBASE-R PCS
WorkOS

workos.com sponsored

The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

SystemVerilog Ethernet related posts

A simple high-throughput open-source packet generator
1 project | /r/FPGA | 12 Jan 2023
Xilinx alternatives??
1 project | /r/FPGA | 22 Oct 2022
The Network Development Kit for FPGA cards in version 0.3.1 released
1 project | /r/FPGA | 22 Sep 2022
custom 10Gbase-R
1 project | /r/FPGA | 27 Aug 2021

Index

	Project	Stars
1	simple10GbaseR	4

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