ravenoc
axi
| ravenoc | axi | |
|---|---|---|
| 1 | 3 | |
| 125 | 930 | |
| - | 3.0% | |
| 4.3 | 6.1 | |
| 10 months ago | 5 days ago | |
| SystemVerilog | SystemVerilog | |
| MIT License | GNU General Public License v3.0 or later |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
ravenoc
axi
- AXI InterConnect
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Any recommendations for an RTL "standard library"?
Hi, I’m one of the developers of basejump. It’s pretty awesome, especially if you’re targeting ASIC. Nearly all the components have been through multiple advanced node tapeouts. The only weakness I see is a lack of AXI components. So I may suggest https://github.com/pulp-platform/axi to supplement
- How to compare HDL simulation/implementation results to Matlab?
What are some alternatives?
AXI4 - AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
chisel - Chisel: A Modern Hardware Design Language
friscv - RISCV CPU implementation in SystemVerilog
nmigen - A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
Cores-VeeR-EL2 - VeeR EL2 Core
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
opentitan - OpenTitan: Open source silicon root of trust
qemu - Xilinx's fork of Quick EMUlator (QEMU) with improved support and modelling for the Xilinx platforms.
Pyverilog - Python-based Hardware Design Processing Toolkit for Verilog HDL
tiny-cores - Collection of assorted small cores
myhdl - The MyHDL development repository