ravenoc
Cores-VeeR-EL2
Our great sponsors
| ravenoc | Cores-VeeR-EL2 | |
|---|---|---|
| 1 | 1 | |
| 121 | 222 | |
| - | 4.1% | |
| 4.3 | 9.2 | |
| 10 months ago | 9 days ago | |
| SystemVerilog | SystemVerilog | |
| MIT License | Apache License 2.0 |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
ravenoc
Cores-VeeR-EL2
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Anandtech: "IBM Power10 Coming To Market: E1080 for 'Frictionless Hybrid Cloud Experiences'"
Including Western Digital's cores used in their SSD controllers: https://github.com/chipsalliance/Cores-SweRV https://github.com/chipsalliance/Cores-SweRV-EL2
What are some alternatives?
AXI4 - AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
riscv-boom - SonicBOOM: The Berkeley Out-of-Order Machine
friscv - RISCV CPU implementation in SystemVerilog
Cores-VeeR-EH1 - VeeR EH1 core
projf-explore - Project F brings FPGAs to life with exciting open-source designs you can build on.
cv32e40p - CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
rocket-chip - Rocket Chip Generator
VeriGPU - OpenSource GPU, in Verilog, loosely based on RISC-V ISA
scr1 - SCR1 is a high-quality open-source RISC-V MCU core in Verilog
WDMC-Ex2-Ultra - Enhanced Ram Disk and Linux Kernel for WD My Cloud Ex2 Ultra
rggen-sv-rtl - Common SystemVerilog RTL modules for RgGen
axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication