open-register-design-tool
FPGA-SDcard-Reader
| open-register-design-tool | FPGA-SDcard-Reader | |
|---|---|---|
| 2 | 1 | |
| 182 | 213 | |
| 1.6% | - | |
| 5.3 | 3.8 | |
| 9 months ago | 8 months ago | |
| Verilog | Verilog | |
| Apache License 2.0 | GNU General Public License v3.0 only |
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open-register-design-tool
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Thoughts about SystemRDL ?
I have used this compiler (https://github.com/Juniper/open-register-design-tool/wiki/Running-Ordt) to generate a Python model to access registers (I use Python on embedded Linux to read/write registers over SPI to the device).
- Auto Generate Header Files
FPGA-SDcard-Reader
What are some alternatives?
rggen - Code generation tool for control and status registers
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
livehd - Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
gf180mcu-pdk - PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).
OpenROAD - OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
PeakRDL-html - Generate address space documentation HTML from compiled SystemRDL input
sdspi - SD-Card controller, using either SPI, SDIO, or eMMC interfaces
OpenTimer - A High-performance Timing Analysis Tool for VLSI Systems
axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
biriscv - 32-bit Superscalar RISC-V CPU
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.