| filament | serv | |
|---|---|---|
| 3 | 20 | |
| 129 | 1,263 | |
| 4.7% | - | |
| 8.7 | 7.6 | |
| 5 days ago | about 1 month ago | |
| Verilog | Verilog | |
| MIT License | ISC License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
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For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
filament
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Engineer creates CPU from scratch in two weeks – begins work on GPUs
Verilog is kind of trash by modern standards. Unfortunately we are stuck with it (well SystemVerilog) until tool vendors support something else.
It's kind of a similar situation to JavaScript actually. And in a similar way, you can compile to Verilog, but just like with JS it makes debugging much more painful.
There was this interesting project but it seems inactive: https://llhd.io/
There's also various alternative HDLs that seem to have various levels of solving the wrong problem (SpinalHDL, MyHDL, Chisel). This one looks quite interesting though: https://filamenthdl.com/
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Filament – A Language for Fearless Hardware Design
It's under /apps in the repo: https://github.com/cucapra/filament/tree/f5da227a059f181b996...
serv
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RISC-V support in Android just got a big setback
> Right now, most devices on the market do not support the C extension
This is not true and easily verifiable.
The C extension is defacto required, the only cores that don't support it are special purpose soft cores.
C extension in the smallest IP available core https://github.com/olofk/serv?tab=readme-ov-file
Supports M and C extensions https://github.com/YosysHQ/picorv32
Another sized optimized core with C extension support https://github.com/lowrisc/ibex
C extension in the 10 cent microcontroller https://www.wch-ic.com/products/CH32V003.html
This one should get your goat, it implements as much as it can using only compressed instructions https://github.com/gsmecher/minimax
- SERV – The SErial RISC-V CPU
- SERV: A bit-serial RISC-V core
- SERV – open-source Tiny SErial RISC-V CPU
- How many LUT for an 8 bit CPU?
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Minimax: a Compressed-First, Microcoded RISC-V CPU
In short: it works, though the implementation lacks the crystal clarity of FemtoRV32 and PicoRV32. The core is larger than SERV but has higher IPC and (very arguably) a more conventional implementation. The compressed instruction set is easier to expand into regular RV32I instructions than it is to execute directly.
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Apple to Move a Part of Its Embedded Cores to RISC-V
https://github.com/olofk/serv
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I have created a Reddit community about PicoBlaze soft processor...
As for the size advantage: this mattered more when LUTs were precious and when PicoBlaze's competition was either similarly unorthodox (J1 Forth CPU) or several times larger (MicroBlaze). Nowadays, there are very small RISC-V cores like FemtoRV32 Quark or SERV. RISC-V benefits from mainstream open-source tooling and has momentum that's hard to beat.
- Microchip to develop 12-core RISC-V processor for NASA
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RISC-V announces first new specifications of 2022 adding to 16 ratified in 2021
The RISC-V spec does allow non-trapping behavior and SeRV in particular has non-trapping behavior, which is an important part of how it can fit into 200 4-input LUTs.
https://github.com/olofk/serv#good-to-know
What are some alternatives?
hdl - HDL libraries and projects
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
riscv-cores-list - RISC-V Cores, SoC platforms and SoCs
IronOS - Open Source Soldering Iron firmware
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
neo430 - :computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
psram-tang-nano-9k - An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA
edalize - An abstraction library for interfacing EDA tools
riscv_verilator_model - RISCV model for Verilator/FPGA targets
zipversa - A Versa Board implementation using the AutoFPGA/ZipCPU infrastructure
minimax - Minimax: a Compressed-First, Microcoded RISC-V CPU
OpenTimer - A High-performance Timing Analysis Tool for VLSI Systems