serv
riscv_verilator_model
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| serv | riscv_verilator_model | |
|---|---|---|
| 16 | 2 | |
| 911 | 30 | |
| - | - | |
| 6.5 | 0.0 | |
| about 1 month ago | over 3 years ago | |
| Verilog | C | |
| ISC License | Apache License 2.0 |
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serv
- How many LUT for an 8 bit CPU?
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Minimax: a Compressed-First, Microcoded RISC-V CPU
In short: it works, though the implementation lacks the crystal clarity of FemtoRV32 and PicoRV32. The core is larger than SERV but has higher IPC and (very arguably) a more conventional implementation. The compressed instruction set is easier to expand into regular RV32I instructions than it is to execute directly.
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Apple to Move a Part of Its Embedded Cores to RISC-V
https://github.com/olofk/serv
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I have created a Reddit community about PicoBlaze soft processor...
As for the size advantage: this mattered more when LUTs were precious and when PicoBlaze's competition was either similarly unorthodox (J1 Forth CPU) or several times larger (MicroBlaze). Nowadays, there are very small RISC-V cores like FemtoRV32 Quark or SERV. RISC-V benefits from mainstream open-source tooling and has momentum that's hard to beat.
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RISC-V announces first new specifications of 2022 adding to 16 ratified in 2021
The RISC-V spec does allow non-trapping behavior and SeRV in particular has non-trapping behavior, which is an important part of how it can fit into 200 4-input LUTs.
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looking for 16 bit RISC ISA to implement on cyclon IV FPGA
SERV has an RV32I ISA. It is really light. I am sure it will fit.
- Risc-v with minimum number of gates
- Olof Kindgren on LinkedIn: We have a new world record! 6000 RISC-V cores in a single chip!
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RISCV sim through Verilator
I have tested SERV on Verilator. It was working without any problems.
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Glacial – microcoded RISC-V core designed for low FPGA resource utilization
Along the same lines of minimizing the amount of logic used at the cost of cycles, there's SERV which uses a bit-serial implementation with a 1-bit data path: https://github.com/olofk/serv
From time to time, I have been tempted to design a RISC-V implementation out of discrete TTL components. Sure, there are plenty of projects out there to build your own processor from scratch, but most of them aren't LLVM targets!
The 32-bit datapaths and need for so many registers makes it a bit daunting to approach directly. That approach would probably end up similar in scale to a MIPS implementation I once saw done like that. (Can't find the link, but it was about half a dozen A4-sized PCBs).
Retreating to an 8-bit microcoded approach and lifting all the registers and complexity into RAM and software is a very attractive idea. It's not like it would ever be a speed demon, either way.
riscv_verilator_model
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RISCV sim through Verilator
So far I have found only this repo : https://github.com/aignacio/riscv_verilator_model.git (does not work for me yet)
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Need help in CPU design
https://github.com/aignacio/riscv_verilator_model Good start...
What are some alternatives?
neorv32 - 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
riscv-cores-list - RISC-V Cores, SoC platforms and SoCs
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
edalize - An abstraction library for interfacing EDA tools
zipversa - A Versa Board implementation using the AutoFPGA/ZipCPU infrastructure
ContrAlto - This repository contains the source code for Living Computers: Museum+Labs's Xerox Alto emulator, ContrAlto.
IronOS - Open Source Soldering Iron firmware for Miniware and Pinecil
OpenTimer - A High-performance Timing Analysis Tool for VLSI Systems
glacial - Glacial - microcoded RISC-V core designed for low FPGA resource utilization
neo430 - :computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
panologic - PanoLogic Zero Client G1 reverse engineering info