serv
riscv_verilator_model
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| serv | riscv_verilator_model | |
|---|---|---|
| 19 | 2 | |
| 1,234 | 40 | |
| - | - | |
| 7.7 | 0.0 | |
| 10 days ago | over 4 years ago | |
| Verilog | C | |
| ISC License | Apache License 2.0 |
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serv
- SERV – The SErial RISC-V CPU
- SERV: A bit-serial RISC-V core
- SERV – open-source Tiny SErial RISC-V CPU
- How many LUT for an 8 bit CPU?
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Minimax: a Compressed-First, Microcoded RISC-V CPU
In short: it works, though the implementation lacks the crystal clarity of FemtoRV32 and PicoRV32. The core is larger than SERV but has higher IPC and (very arguably) a more conventional implementation. The compressed instruction set is easier to expand into regular RV32I instructions than it is to execute directly.
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Apple to Move a Part of Its Embedded Cores to RISC-V
https://github.com/olofk/serv
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I have created a Reddit community about PicoBlaze soft processor...
As for the size advantage: this mattered more when LUTs were precious and when PicoBlaze's competition was either similarly unorthodox (J1 Forth CPU) or several times larger (MicroBlaze). Nowadays, there are very small RISC-V cores like FemtoRV32 Quark or SERV. RISC-V benefits from mainstream open-source tooling and has momentum that's hard to beat.
- Microchip to develop 12-core RISC-V processor for NASA
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RISC-V announces first new specifications of 2022 adding to 16 ratified in 2021
The RISC-V spec does allow non-trapping behavior and SeRV in particular has non-trapping behavior, which is an important part of how it can fit into 200 4-input LUTs.
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Efinix and Xyloni Board - Heard a lot of clients mention them, so took a look.
It will be interesting to see if a Serv will fit with some usable gates left over.
riscv_verilator_model
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RISCV sim through Verilator
So far I have found only this repo : https://github.com/aignacio/riscv_verilator_model.git (does not work for me yet)
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Need help in CPU design
https://github.com/aignacio/riscv_verilator_model Good start...
What are some alternatives?
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
riscv-cores-list - RISC-V Cores, SoC platforms and SoCs
gdb-stub - gdb-proxy implementation for bonfire
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
picoMIPS - picoMIPS processor doing affine transformation
IronOS - Open Source Soldering Iron firmware
psram-tang-nano-9k - An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA
neo430 - :computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
edalize - An abstraction library for interfacing EDA tools
zipversa - A Versa Board implementation using the AutoFPGA/ZipCPU infrastructure
minimax - Minimax: a Compressed-First, Microcoded RISC-V CPU