serv
minimax
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serv | minimax | |
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19 | 13 | |
1,244 | 194 | |
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7.7 | 5.8 | |
16 days ago | 8 months ago | |
Verilog | Verilog | |
ISC License | BSD 3-clause "New" or "Revised" License |
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serv
- SERV – The SErial RISC-V CPU
- SERV: A bit-serial RISC-V core
- SERV – open-source Tiny SErial RISC-V CPU
- How many LUT for an 8 bit CPU?
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Minimax: a Compressed-First, Microcoded RISC-V CPU
In short: it works, though the implementation lacks the crystal clarity of FemtoRV32 and PicoRV32. The core is larger than SERV but has higher IPC and (very arguably) a more conventional implementation. The compressed instruction set is easier to expand into regular RV32I instructions than it is to execute directly.
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Apple to Move a Part of Its Embedded Cores to RISC-V
https://github.com/olofk/serv
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I have created a Reddit community about PicoBlaze soft processor...
As for the size advantage: this mattered more when LUTs were precious and when PicoBlaze's competition was either similarly unorthodox (J1 Forth CPU) or several times larger (MicroBlaze). Nowadays, there are very small RISC-V cores like FemtoRV32 Quark or SERV. RISC-V benefits from mainstream open-source tooling and has momentum that's hard to beat.
- Microchip to develop 12-core RISC-V processor for NASA
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RISC-V announces first new specifications of 2022 adding to 16 ratified in 2021
The RISC-V spec does allow non-trapping behavior and SeRV in particular has non-trapping behavior, which is an important part of how it can fit into 200 4-input LUTs.
https://github.com/olofk/serv#good-to-know
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Efinix and Xyloni Board - Heard a lot of clients mention them, so took a look.
It will be interesting to see if a Serv will fit with some usable gates left over.
minimax
- Is the 6502 a RISC or CISC processor? (2005)
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A Single-Cycle 64-Bit RISC-V Register File
On FPGAs, a register file probably fits better into distributed RAM than block RAM.
On Xilinx, for example: a 64-bit register file doesn't map efficiently to Xilinx's RAMB36 primitives. You'd need 2 RAMB36 primitives to provide a 64-bit wide memory with 1 write port and 2 read ports, each addressed separately. Only 6% (32 of 512) entries in each RAMB36 are ever addressable. It's this inefficient because ports, not memory cells, are the contented resource and BRAMs geometries aren't that elastic.
A 64-bit register file in distributed RAM, conversely, is a something like an array of DPRAM32 primitives (see, for example, UG474). Each register would still be stored multiple times to provide additional ports, but depending on the fabric, there's less (or no) unaddressed storage cells.
The Minimax RISC-V CPU (https://github.com/gsmecher/minimax; advertisement warning: my project) is what you get if you chase efficient mapping of FPGA memory primitives (both register-file and RAM) to a logical conclusion. Whether this is actually worth hyper-optimizing really depends on the application. Usually, it's not.
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Verilator - Do I need to maintain two testbench suits?
I haven't used it on a huge design (I'm usually a VHDL person), but it was a hassle-free replacement for iverilog when regression testing Minimax. Performance is substantially better; compilation times are worse.
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Zylin ZPU: The worlds smallest 32 bit CPU with GCC toolchain
Note that you can't compare LUT4 results (ZPU @ 440 LUTs) against LUT6 results (PicoRV32 @ 750 LUTs). The ZPU is remarkably small, and it's a bigger gap than a direct comparison shows.
SERV is a fair comparison, since it's architected for 4LUTs and I suspect the synthesis results come from iCE40 tools.
I have a contender in the "very small" space, too [1], although I don't claim it's as mature or complete as SERV. (If Minimax was excluded from your post on the basis of insanity, I'm OK with that.)
[1] https://github.com/gsmecher/minimax
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Senior Design Project Ideas?
I develop Minimax (https://github.com/gsmecher/minimax), an open-source RISC-V implementation. It's currently written in both VHDL and Verilog (the two implementations are equivalent, though I am likely to drop the VHDL implementation if it's too much work to keep them both.)
- Compiled and Interpreted Languages: Two Ways of Saying Tomato
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PicoBlaze in Verilog / Vivado
The best point-of-entry for "tiny" MCUs these days is FemtoRV32-Quark or SERV. I also maintain my own small RISC-V core (Minimax), though it's early on in graduating from "experiment" to "real design".
- Show HN: Minimax – A Compressed-First, Microcoded RISC-V CPU
- Minimax: A Compressed-First, Microcoded RISC-V CPU
What are some alternatives?
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
picorv32 - PicoRV32 - A Size-Optimized RISC-V CPU
riscv-cores-list - RISC-V Cores, SoC platforms and SoCs
ZPUFlex - A highly-configurable and compact variant of the ZPU processor core
IronOS - Open Source Soldering Iron firmware
riscof
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
Artix-7-HDMI-processing - Receiving and processing 1080p HDMI audio and video on the Artix 7 FPGA
neo430 - :computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
mini-rv32ima - A tiny C header-only risc-v emulator.
psram-tang-nano-9k - An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA
sulong - Obsolete repository. Moved to oracle/graal.