biriscv
kianRiscV
| biriscv | kianRiscV | |
|---|---|---|
| 6 | 1 | |
| 749 | 487 | |
| - | - | |
| 0.0 | 7.8 | |
| over 2 years ago | 6 days ago | |
| Verilog | AGS Script | |
| Apache License 2.0 | ISC License |
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biriscv
kianRiscV
-
Have I discovered a synthesis/routing defect with the Gowin IDE?
I encountered this issue when having difficulty porting a risc-v softcore (https://github.com/splinedrive/kianRiscV/blob/master/README.md), which works perfectly on two other hardware platforms. The linux boot process would stall about 1M instructions in. I tracked the issue down to the above issue, which differed from simulation results. Straightforward attempts to recreate the defect in a standalone environment failed. Instead I have resorted to stripping back and refactoring the failing softcore implementation layer by layer until reaching a minimal setup which still exhibits the defect. The result is the code below. The code doesn’t do anything meaningful, except exhibit the defect.
What are some alternatives?
riscv - RISC-V CPU Core (RV32IM)
my_hdmi_device - New clean hdmi implementation for ulx3s, icestick, icoboard, arty7, colorlight i5 and blackicemx! With tmds encoding hacked down from dvi standard. Supports DDR and SRD tranfser!
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
icicle - 32-bit RISC-V system on chip for iCE40 FPGAs
sdspi - SD-Card controller, using either SPI, SDIO, or eMMC interfaces
zipcpu - A small, light weight, RISC CPU soft core
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
vgasim - A Video display simulator
s1-ecg-demo - An all-in-one kit to deploy and test ECG algorithms with ease. Based on the AD8233 and S1 Module, this open source board is a great for new products, as well as research and teaching.
wbicapetwo - Wishbone to ICAPE interface conversion
a2o - The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution (register renaming, reservation stations, completion buffer) and a store queue. It is now being updated for compliancy and integration into open projects.