basejump_stl
axi
| basejump_stl | axi | |
|---|---|---|
| 4 | 3 | |
| 447 | 930 | |
| 2.0% | 3.0% | |
| 6.2 | 6.1 | |
| about 1 month ago | 3 days ago | |
| SystemVerilog | SystemVerilog | |
| GNU General Public License v3.0 or later | GNU General Public License v3.0 or later |
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basejump_stl
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Extra-wide aspect ratio FIFO in Vivado?
BaseJump STL ( https://github.com/bespoke-silicon-group/basejump_stl ) has lots of these plumbing modules, silicon-validated several times
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Cross module reference (XMR)?
It depends on your mapping algorithm and whether the tools you’re looking at supported mixed-language synthesis, but you can always use our battle-tested components for these kind of functions: https://github.com/bespoke-silicon-group/basejump_stl
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Any recommendations for an RTL "standard library"?
https://github.com/bespoke-silicon-group/basejump_stl maybe?
- Data flow ternary vs behavioral case statements
axi
- AXI InterConnect
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Any recommendations for an RTL "standard library"?
Hi, I’m one of the developers of basejump. It’s pretty awesome, especially if you’re targeting ASIC. Nearly all the components have been through multiple advanced node tapeouts. The only weakness I see is a lack of AXI components. So I may suggest https://github.com/pulp-platform/axi to supplement
- How to compare HDL simulation/implementation results to Matlab?
What are some alternatives?
chisel - Chisel: A Modern Hardware Design Language
opentitan - OpenTitan: Open source silicon root of trust
nmigen - A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
PipelineC - A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
surf - A huge VHDL library for FPGA development
qemu - Xilinx's fork of Quick EMUlator (QEMU) with improved support and modelling for the Xilinx platforms.
satcat5 - SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.
Pyverilog - Python-based Hardware Design Processing Toolkit for Verilog HDL