basejump_stl
PipelineC
| basejump_stl | PipelineC | |
|---|---|---|
| 4 | 46 | |
| 447 | 544 | |
| 2.0% | - | |
| 6.2 | 9.5 | |
| about 1 month ago | about 13 hours ago | |
| SystemVerilog | Python | |
| GNU General Public License v3.0 or later | GNU General Public License v3.0 only |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
basejump_stl
-
Extra-wide aspect ratio FIFO in Vivado?
BaseJump STL ( https://github.com/bespoke-silicon-group/basejump_stl ) has lots of these plumbing modules, silicon-validated several times
-
Cross module reference (XMR)?
It depends on your mapping algorithm and whether the tools you’re looking at supported mixed-language synthesis, but you can always use our battle-tested components for these kind of functions: https://github.com/bespoke-silicon-group/basejump_stl
-
Any recommendations for an RTL "standard library"?
https://github.com/bespoke-silicon-group/basejump_stl maybe?
- Data flow ternary vs behavioral case statements
PipelineC
-
PipelineC Example: FM Radio Demodulation (FPGA SDR)
Related: PipelineC: A C-like hardware description language (HDL):
https://github.com/JulianKemmerer/PipelineC
- Generate non-CPU FPGA circuits from a C-like language
- What makes C, Verilog, Java, Python, etc. so different?
-
What are your private FPGA projects and why?
https://github.com/JulianKemmerer/PipelineC :)
-
What's the right path to learning for someone coming from software?
However, I think its still possible to have a productive C->HDL journey. Check out PipelineC, https://github.com/JulianKemmerer/PipelineC, its meant for folks with C experience to get right into doing RTL style reasoning :)
- Seeking Advice on How to approch RTL Programming
-
Using FPGAs for computations as a beginner
https://github.com/JulianKemmerer/PipelineC-Graphics/blob/main/doc/Sphery-vs-Shapes.pdf https://github.com/JulianKemmerer/PipelineC
-
Generating pipeline stages automatically?
This is exactly what the PipelineC tool was made for. https://github.com/JulianKemmerer/PipelineC
- Does Xilinx use multiplication algorithms to speed up/reduce the multipliers size?
- Sphery vs. Shapes, the first raytraced game that is not software
What are some alternatives?
chisel - Chisel: A Modern Hardware Design Language
pygears - HW Design: A Functional Approach
opentitan - OpenTitan: Open source silicon root of trust
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
surf - A huge VHDL library for FPGA development
pycparser - :snake: Complete C99 parser in pure Python
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
nngen - NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network
satcat5 - SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.
hls4ml - Machine learning on FPGAs using HLS
tiny-cores - Collection of assorted small cores
antikernel - The Antikernel operating system project