axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication (by pulp-platform)
qemu
Xilinx's fork of Quick EMUlator (QEMU) with improved support and modelling for the Xilinx platforms. (by Xilinx)
| axi | qemu | |
|---|---|---|
| 3 | 1 | |
| 930 | 225 | |
| 3.0% | 1.8% | |
| 6.1 | 4.0 | |
| 7 days ago | 7 days ago | |
| SystemVerilog | C | |
| GNU General Public License v3.0 or later | GNU General Public License v3.0 or later |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
axi
Posts with mentions or reviews of axi.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-06-28.
- AXI InterConnect
-
Any recommendations for an RTL "standard library"?
Hi, I’m one of the developers of basejump. It’s pretty awesome, especially if you’re targeting ASIC. Nearly all the components have been through multiple advanced node tapeouts. The only weakness I see is a lack of AXI components. So I may suggest https://github.com/pulp-platform/axi to supplement
- How to compare HDL simulation/implementation results to Matlab?
qemu
Posts with mentions or reviews of qemu.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-06-01.
-
How to compare HDL simulation/implementation results to Matlab?
I'd probably simulate both the accelerator and the AXI wrapper. One could instantiate a risc-v core to drive the AXI bus under simulation. gem5 or qemu see the Xilinx fork with AXI support.
What are some alternatives?
When comparing axi and qemu you can also consider the following projects:
chisel - Chisel: A Modern Hardware Design Language
tpm2-tss - OSS implementation of the TCG TPM2 Software Stack (TSS2)
nmigen - A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
pyverilator - Python wrapper for verilator model
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
kvm-guest-drivers-windows - Windows paravirtualized drivers for QEMU\KVM
opentitan - OpenTitan: Open source silicon root of trust
Pyverilog - Python-based Hardware Design Processing Toolkit for Verilog HDL
keyforge-burger-inserts - Keyforge Deckbox Inserts
Cores-VeeR-EL2 - VeeR EL2 Core