axi VS Pyverilog

Compare axi vs Pyverilog and see what are their differences.

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication (by pulp-platform)
axi Axi4 axi4-lite Systemverilog Hardware network-on-chip Asic Fpga Rtl IP
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Pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL (by PyHDI)
verilog-hdl Hardware Compiler Parser dataflow-analyzer control-flow-analyzer Code-Generator Python
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axi Pyverilog
3 2
930 573
3.0% 1.4%
6.1 0.0
6 days ago 9 months ago
SystemVerilog Python
GNU General Public License v3.0 or later Apache License 2.0
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
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For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

axi

Posts with mentions or reviews of axi. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-06-28.

Pyverilog

Posts with mentions or reviews of Pyverilog. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-03-26.
  • Tools for designing hardware in Python
    6 projects | /r/Python | 26 Mar 2022
    Any hardware designers here who use Python for designing hardware? There are a bunch of libraries that all seem promising MyHDL, PyRTL, PyVerilog, PyLog, PyMTL3, ... All seem to work roughly the same. Write code in Python and transpile it to VHDL/Verilog. Which of these are popular and well-maintained? MyHDL looks good but it's last release was 0.10 in 2018 and for hardware design you don't want to rely on 0.x software. Anything like Chisel for Python.
  • How to compare HDL simulation/implementation results to Matlab?
    6 projects | /r/FPGA | 1 Jun 2021
    PyVerilog https://github.com/PyHDI/Pyverilog

What are some alternatives?

When comparing axi and Pyverilog you can also consider the following projects:

chisel - Chisel: A Modern Hardware Design Language

pyverilator - Python wrapper for verilator model

nmigen - A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen

myhdl - The MyHDL development repository

fusesoc - Package manager and build abstraction tool for FPGA/ASIC development

PyRTL - A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extendability rather than performance or optimization is the overarching goal.

opentitan - OpenTitan: Open source silicon root of trust

datamodel-code-generator - Pydantic model and dataclasses.dataclass generator for easy conversion of JSON, OpenAPI, JSON Schema, and YAML data sources.

qemu - Xilinx's fork of Quick EMUlator (QEMU) with improved support and modelling for the Xilinx platforms.

Cores-VeeR-EL2 - VeeR EL2 Core

nngen - NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network

axi vs chisel Pyverilog vs pyverilator axi vs nmigen Pyverilog vs myhdl axi vs fusesoc Pyverilog vs PyRTL axi vs opentitan Pyverilog vs datamodel-code-generator axi vs qemu Pyverilog vs nmigen axi vs Cores-VeeR-EL2 Pyverilog vs nngen