wb2axip
vunit
wb2axip | vunit | |
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51 | 10 | |
433 | 684 | |
- | 0.9% | |
3.1 | 8.2 | |
4 months ago | about 1 month ago | |
Verilog | VHDL | |
- | GNU General Public License v3.0 or later |
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wb2axip
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Simple skid buffer implementation
I've always been partial to my own skidbuffer article and implementation. (You'd expect me to be, they're my own ...) I get your point, though, about some applications needing a registered output. I've come across many, as requirements change from one project to the next. This is why, in my own implementation, I have parameters allowing me to adjust which implementation I'm using. In this case in particular, I have a parameter adjusting whether or not the output is registered. (The outgoing READY signal, though, is always registered--that's the point of the skid buffer in the first place, and what keeps it from being a regular buffer.)
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Testing Axi Slaves in Simulation
Ref: [1], [2]
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Looking to implimenting an autocorrelation function (ACF) into one of my projects.
Have you considered this article? It goes over the basics of the autocorrelation function, while also illustrating how you can build one with a Wishbone interface. Further, the Verilator logic for this function is kept and maintained on github here. Sure, it uses Wishbone. If you want to use AXI you can either use a bridge, or rework the the interface (it's not that hard ...).
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Guys can u send me some github repositories on some simple project on system verilog with functionality like with couple functions ? Its my first reddit post in my life.
If this is what you want, though, then consider checking out the apply_wstrb function in my wb2axip repository. Perhaps the easyaxil might be the easiest one to start with.
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Reference of verification IPs
The worst thing that can happen on a bus is a protocol error that causes the device to lock up. Sadly, such errors have been common when using AXI or AXI-Lite--especially since traditional "verification IP" bus models won't catch all circumstances. This is why I make a general (personal) rule that nothing should touch a bus unless it has been formally verified. This check basically guarantees that every bus request gets one (and only one) response. It's not sufficient to verify an IP fully, but it's a good start. You can find my formal verification models for AXI-Lite, Wishbone, and (to some extent) Avalon in this repository. I've also been known to make my full AXI model available to Patreon sponsors of my blog.
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A simple AXI-Lite register file
As an experiment, I tried a formal first approach using u/ZipCPU's faxil_slave.v.
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AXI-Lite register bank revisited
I then moved on to an internal desk check of the design ... 1. skydivertricky is right: AXI does not allow timeouts. If you implement an AXI timeout, you will risk crashing any system using your design. Your timeout implementation is therefore broken, and will risk crashing any system attempting to interact with your design. This applies to both your read and write paths. 2. Sure enough, your write state machine looks only for the write address strobe during the idle state. If write data shows up early, the write data will be forgotten causing the system to hang. This was one of the bugs caught by SymbiYosys and mentioned above. 3. Your design has a nasty sequencing bug within it: wren is set on the clock _after the transaction takes place. As a result, the s_axi_awaddr and s_axi_wdata values used within your design may contain garbage within them. Indeed, they may be already set for the next transaction, or the master may put some other value in them. As a result, writes to your design may work for some masters, or more likely will not work at all. (They won't work with any of my own open source AXI-lite masters.) 4. I would recommend implementing WSTRB. There are plenty of implementations out there that will use this value, particularly when crossing from one bus width to another, but also when the CPU attempts to write less than a full word. I've been burned more than once by acting on a write when WSTRB was zero. 5. As predicted by SymbiYosys, your read data calculation is also broken. Specifically, it depends upon the value in ARADDR on the cycle following the cycle where ARVALID && ARREADY. This breaks protocol, and is likely to give you some very unexpected results. 6. While not technically broken, I would recommend that your reads ignore the bottom two bits of address. If you do this, the reads will then work if the CPU issues a load-byte or load-halfword instruction. The same applies to the writes--you should be looking at all but the bottom two bits (for a bus with 32-bit data words, like AXI-lite).
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Xilinx FIFO generator for skid buffer?
Can a FIFO be generated to use the AXI stream protocol? Absolutely! Check out this FIFO: - S_AXIS_VALID can be fed to the write port, i_wr - S_AXIS_READY is the compliment of the FIFO full output, o_full - S_AXIS_DATA can be fed to the incoming data port, i_data - M_AXIS_VALID is the compliment of the FIFO empty output, o_emtpy - M_AXIS_READY can be fed directly to the read port, i_rd - M_AXIS_DATA can be read directly from the outgoing data port, o_data - If you want to support other AXI Stream signals, they can simply be concatenated with the data signals above.
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Connecting custom IP to microblaze
I recently connected my own IP to a Microblaze core via the AXI-lite interface. Vivado has a tool to generate AXI IP, but it's broken so I used this implementation of an AXI-lite slave. It comes with some registers that'll be accessible in the processors address space. Here is a more detailed explanation of the linked implementation.
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Implement Synchronous FWFT FIFO in BRAM
Here's an example of an FWFT FIFO written in a vendor independent fashion. Yes, it requires a bit of wizardry to get right--primarily in how the read address is calculated, but I've used it for years now and it's held up nicely for me.
vunit
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Software languages vs HDLs for verification
My goto tools for verification in VHDL are UVVM and VUnit
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Libero - Inefficient Simulations
I think the VUnit vivado example (https://github.com/VUnit/vunit/tree/master/examples/vhdl/vivado) may be a good starting point when working with Xilinx IP outside of an IDE.
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Books About Testing and Verification
I learned a lot from https://vunit.github.io/ I even became a better VHDL engineer from this fantastic project. It showed me things I did not know VHDL was capable of.
- A couple of questions for the experts
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Reference of verification IPs
Hey! I haven't seen anyone mention Vunit yet. Vunit has a verification components library with Master and Slave components for a decent amount of buses: Axi, Axi stream, Wishbone, Avalon, Uart. The code isn't 100% bullet proof but it is really useful for testing designs.
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SystemVerilog testbench library
I agree vunit is great but due to circumstances (you can see post above) I need the testbench to be purely SV (and vunit as you said wouldn't help with all of that, only some of it, as you have pointed out). When I refered to vunit I forgot to link the example: https://github.com/VUnit/vunit/tree/master/examples/verilog/uart/src . I referred more to tge fact it is self checking, and the tasks can be reused in ither tbs as well
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The Vivado 2021.2 is out thread
As for simulation, the last time I used it there were a lot of features not supported. Not sure where this is documented, but I know VUnit can't support it per https://github.com/VUnit/vunit/issues/209 .
- How do you do automated testing of your HDL?
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VHDL Testbench Library Comparison
Please consider adding simulator support to this comparison. For example, Vivado's xsim can't be used with VUnit.
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The simplest way to automate my testbench?
I think these two examples can help you get started. https://github.com/VUnit/vunit/tree/master/examples/vhdl/array_axis_vcs https://github.com/VUnit/vunit/tree/master/examples/vhdl/generate_tests/
What are some alternatives?
wavedrom - :ocean: Digital timing diagram rendering engine
spi-fpga - SPI master and SPI slave for FPGA written in VHDL
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
AXI4 - AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
verilog-axi - Verilog AXI components for FPGA implementation
ghdl - VHDL 2008/93/87 simulator
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
zipcpu - A small, light weight, RISC CPU soft core
catapult-v3-smartnic-re - Documenting the Catapult v3 SmartNIC FPGA boards (Dragontails Peak & Longs Peak)
axidmacheck - AXI DMA Check: A utility to measure DMA speeds in simulation
OsvvmLibraries - Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.