riscv
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riscv | livehd | |
---|---|---|
2 | 1 | |
1,040 | 197 | |
- | 1.0% | |
1.8 | 9.2 | |
over 2 years ago | 1 day ago | |
Verilog | Verilog | |
BSD 3-clause "New" or "Revised" License | GNU General Public License v3.0 or later |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
riscv
-
Ultraembedded RISCV Module
I have been trying to execute some instructions to the ultraembedded riscv module https://github.com/ultraembedded/riscv
- I made my own silicon chip: Project Silicon Rider
livehd
What are some alternatives?
biriscv - 32-bit Superscalar RISC-V CPU
hdl - HDL libraries and projects
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
open-register-design-tool - Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
zipcpu - A small, light weight, RISC CPU soft core
serv - SERV - The SErial RISC-V CPU
Toast-RV32i - Pipelined RISC-V RV32I Core in Verilog
cpu11 - Revengineered ancient PDP-11 CPUs, originals and clones
uhd - The USRP™ Hardware Driver Repository
riscv-cores-list - RISC-V Cores, SoC platforms and SoCs