riscv
livehd
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| riscv | livehd | |
|---|---|---|
| 1 | 1 | |
| 742 | 172 | |
| - | 3.5% | |
| 1.0 | 5.3 | |
| over 1 year ago | 7 days ago | |
| Verilog | Verilog | |
| BSD 3-clause "New" or "Revised" License | GNU General Public License v3.0 or later |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
riscv
We haven't tracked posts mentioning riscv yet.
Tracking mentions began in Dec 2020.
livehd
We haven't tracked posts mentioning livehd yet.
Tracking mentions began in Dec 2020.
What are some alternatives?
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darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Toast-RV32i - Pipelined RISC-V RV32I Core in Verilog
hdl - HDL libraries and projects
open-register-design-tool - Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
ice40_power - Power analysis of the ICE40UP5K-SG48 devices
uhd - The USRP™ Hardware Driver Repository
riscv-cores-list - RISC-V Cores, SoC platforms and SoCs
psram-tang-nano-9k - An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA
cpu11 - Revengineered ancient PDP-11 CPUs, originals and clones