livehd VS open-register-design-tool

Compare livehd vs open-register-design-tool and see what are their differences.

livehd

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation (by masc-ucsc)

open-register-design-tool

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input (by Juniper)
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livehd open-register-design-tool
1 2
166 158
1.8% 1.3%
8.9 0.0
2 days ago 3 months ago
Verilog Verilog
GNU General Public License v3.0 or later Apache License 2.0
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

livehd

Posts with mentions or reviews of livehd. We have used some of these posts to build our list of alternatives and similar projects.

We haven't tracked posts mentioning livehd yet.
Tracking mentions began in Dec 2020.

open-register-design-tool

Posts with mentions or reviews of open-register-design-tool. We have used some of these posts to build our list of alternatives and similar projects.

We haven't tracked posts mentioning open-register-design-tool yet.
Tracking mentions began in Dec 2020.

What are some alternatives?

When comparing livehd and open-register-design-tool you can also consider the following projects:

rggen - Code generation tool for configuration and status registers

gf180mcu-pdk - PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).

hdl - HDL libraries and projects

openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

PeakRDL-html - Generate address space documentation HTML from compiled SystemRDL input

cpu11 - Revengineered ancient PDP-11 CPUs, originals and clones

riscv - RISC-V CPU Core (RV32IM)

biriscv - 32-bit Superscalar RISC-V CPU

OpenTimer - A High-performance Timing Analysis Tool for VLSI Systems

serv - SERV - The SErial RISC-V CPU