livehd
biriscv
Our great sponsors
| livehd | biriscv | |
|---|---|---|
| 1 | 5 | |
| 166 | 505 | |
| 0.0% | - | |
| 8.4 | 0.0 | |
| 6 days ago | over 1 year ago | |
| Verilog | Verilog | |
| GNU General Public License v3.0 or later | Apache License 2.0 |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
livehd
We haven't tracked posts mentioning livehd yet.
Tracking mentions began in Dec 2020.
biriscv
We haven't tracked posts mentioning biriscv yet.
Tracking mentions began in Dec 2020.
What are some alternatives?
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
riscv - RISC-V CPU Core (RV32IM)
sdspi - SD-Card controller, using a SPI interface that is (optionally) shared
zipcpu - A small, light weight, RISC CPU soft core
hdl - HDL libraries and projects
vgasim - A Video display simulator
open-register-design-tool - Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
wbicapetwo - Wishbone to ICAPE interface conversion
dpll - A collection of phase locked loop (PLL) related projects
cpu11 - Revengineered ancient PDP-11 CPUs, originals and clones