livehd
Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation (by masc-ucsc)
cpu11
Revengineered ancient PDP-11 CPUs, originals and clones (by 1801BM1)
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| livehd | cpu11 | |
|---|---|---|
| 1 | 2 | |
| 197 | 146 | |
| 1.0% | - | |
| 9.2 | 5.3 | |
| 1 day ago | 4 months ago | |
| Verilog | Verilog | |
| GNU General Public License v3.0 or later | GNU General Public License v3.0 or later |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
livehd
Posts with mentions or reviews of livehd.
We have used some of these posts to build our list of alternatives
and similar projects.
cpu11
Posts with mentions or reviews of cpu11.
We have used some of these posts to build our list of alternatives
and similar projects.
- Dec F11 precise replica in Verilog, based on reverse engineering of real dies
-
I finally got a PDP-8i (sort of).
There are quite a few HDL implementations, eg CPU11 and this list.
What are some alternatives?
When comparing livehd and cpu11 you can also consider the following projects:
hdl - HDL libraries and projects
PDP-11 - A collection of PDP-11 related files
riscv - RISC-V CPU Core (RV32IM)
open-fpga-verilog-tutorial - Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
open-register-design-tool - Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
serv - SERV - The SErial RISC-V CPU
biriscv - 32-bit Superscalar RISC-V CPU
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
zipcpu - A small, light weight, RISC CPU soft core