open-fpga-verilog-tutorial
Learn how to design digital systems and synthesize them into an FPGA using only opensource tools (by Obijuan)
zipcpu
A small, light weight, RISC CPU soft core (by ZipCPU)
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open-fpga-verilog-tutorial | zipcpu | |
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3 | 13 | |
743 | 1,190 | |
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0.0 | 6.3 | |
about 4 years ago | about 1 month ago | |
Verilog | Verilog | |
GNU General Public License v3.0 only | - |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
open-fpga-verilog-tutorial
Posts with mentions or reviews of open-fpga-verilog-tutorial.
We have used some of these posts to build our list of alternatives
and similar projects.
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FPGA for beginners?
The toolchain is called Icestorm, main tool is yosys, most information will be in English. I started with this tutorials here (also in English) https://github.com/Obijuan/open-fpga-verilog-tutorial. Then I used books to learn more on the basics of cpu design in verilog (which can also found online). Obijuan is a Spanish profesor teaching digital electronics in university, he lead the development of a graphical user interface to generate verilog based on a blocks UI, which helps design circuits when you are starting, but unfortunately I believe all his videos are in Spanish, I'd suggest you give it a try even if you don't understand English, as the material available (wiki and videos) is very good. Look for "fpgawars jedi academy " and IceStudio (the tool). But in the end, I personally felt limited by the GUI tool (which was still under heavy development at the time) and went straight to code the verilog code by hand (which obviously is more flexible). Anyway I feel there are not that many pattern to know.
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What's the difference between FPGA, RISC-V, Arduino?
Among your choices, FPGA is the answer. I would suggest a cheap iCE40 board like the iCESugar, to get started. Then follow tutorials targetting ice40+open stack.
- Digital Design for FPGAs, with free tools
zipcpu
Posts with mentions or reviews of zipcpu.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-10-20.
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Xilinx FIFO generator for skid buffer?
For example, my most recent ZipCPU DMA design will (eventually) handle 8b, 16b, 32b, or arbitrary transfer sizes for both reading or writing. This has forced me to place a shim both before and after the FIFO to make it work properly.
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Five legally free FPGA books (plus one about Machine Learning)
The Some Assembly Required series on Youtube has a good walkthrough of implementing a 6502, from scratch. Also, /u//ZipCPU has some good documentation of the CPU he built from scratch, as well as some tutorials, at https://zipcpu.com/ and https://github.com/ZipCPU/zipcpu.
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What make xilinx fpga runs soft core cpu faster than lattice
check out this usage chart for the ZipCPU's logic usage (also linked above). Each line in the chart beginning with Zip represents a different CPU configuration. If the FPGA speeds were the same (they aren't typically), then each configuration line should have the same CPU speed (not counting interconnect, RAM or peripherals). Two of the columns measure iCE40 4-LUTs and Xilinx 6-LUTs.
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OS AXI4 Crossbar with good performance
If you are looking for an AXI4 cache implementation, the ZipCPU currently supports two (I+D) that you might be able to gain some insights from. There's the AXI instruction cache implementation, and an AXI4 data cache implementation. They are both one way caches. Both were featured in an article on performance measurement last year. The data cache implementation doesn't support exclusive access yet--that's still on my to-do list. You can find these caches demonstrated in my AXI DMA check repo, if you'd like to try them out.
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Why is simulation such an important step in the design workflow? Why not just run on actual hardware?
My experience comes from both the ZipCPU (a basic pipelined CPU) and verifying a lot of bus components. I haven't (yet) done an out of order processor, although I will say that verifying a cache gets really basic with formal methods, and I've now verified several cache implementations. The first data cache I wrote took me about two weeks to both write and complete a full formal proof.
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What modules/hardware would you like to see?
I've posted quite a few AXI designs on github. These include an AXI Crossbar, an AX DMA, and even an AXI scatter-gather based DMA. Some of my recent postings even include instruction or [data](instruction caches.
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Using Xilinx AXI Datamover to move DDR memory to FPGA block RAM
Were this my task, I'd write the core myself. I have, for example, an AXI instruction cache you can reference if you'd like and I'm currently building a data cache following this Wishbone example, only for AXI instead. (I was hoping to offer a Zoom call today for anyone interested, where we'd try verifying this new data cache, but ... I didn't get far enough along on the project to do so today. Perhaps next week.()
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[Help] CPU: Changing from BRAM to real program flash
In some of my early CPU tests, one of my earlier instruction fetches would just keep reading up to 16 instructions ahead of time. I thought this was great until I started examining the resulting performance. The first problem was that it wouldn't release the bus for either a data load or store, and the next problem was that the request was so long the result was often irrelevant by the time it arrived since the CPU had already branched away from the addresses it was fetching.
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Can someone help me fix my simulation workflow?
That solution isn't all that satisfying to me, so ... I'm trying to do better. My next attempt is going to be 1) using the ZipCPU instead of the ARM (at least for simulation, and certainly instead of a BFM), 2) using AXI instead of Wishbone (Yes, the ZipCPU can now speak either Wishbone or (mostly) AXI), using my own AXI infrastructure (to get rid of the bridges), and using AutoFPGA to compose the design together and handle addressing requirements (instead of Qsys).
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Soft CPUs - how to debug and test in a sane way?
Yes, the ZipCPU is modular. It consists of several components: a pre-fetch (of which there are several to choose from), an instruction decoder, an ALU, a divide unit, a multiply unit, and a memory unit (of which there are multiple to choose from again). Each unit has its own unit tests (proofs--not simulations).
What are some alternatives?
When comparing open-fpga-verilog-tutorial and zipcpu you can also consider the following projects:
icestudio - :snowflake: Visual editor for open FPGA boards
lxp32-cpu - A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
apio - :seedling: Open source ecosystem for open FPGA boards
openarty - An Open Source configuration of the Arty platform
uhd - The USRP™ Hardware Driver Repository
riscv - RISC-V CPU Core (RV32IM)
FPGA_Asynchronous_FIFO - FIFO implementation with different clock domains for read and write.
wb2axip - Bus bridges and other odds and ends
NTHU-ICLAB - 清華大學 | 積體電路設計實驗 (IC LAB) | 110上
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
interpolation - Digital Interpolation Techniques Applied to Digital Signal Processing
open-fpga-verilog-tutorial vs icestudio
zipcpu vs lxp32-cpu
open-fpga-verilog-tutorial vs apio
zipcpu vs openarty
open-fpga-verilog-tutorial vs uhd
zipcpu vs riscv
open-fpga-verilog-tutorial vs FPGA_Asynchronous_FIFO
zipcpu vs wb2axip
open-fpga-verilog-tutorial vs NTHU-ICLAB
zipcpu vs FPGA_Asynchronous_FIFO
open-fpga-verilog-tutorial vs darkriscv
zipcpu vs interpolation