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As for hooking up the QSPI flash, you're not thinking this through very well. You're going to want to hook your CPU up to the QSPI flash, SDRAM memory, and possibly block RAM as well. That includes both I and D bus interfaces. You'll also likely to want to connect your D interface to several memory mapped peripherals: serial port, GPIO, SD card, etc. That means your going to want a separate bus component to handle all these connections. I originally used a series of arbiters, but eventually found that crossbars were simpler to use and tended to provide better performance. Don't forget you are also likely to want room in your eco-system for an external debug interface to come in and interact with your bus and/or CPU, as well as for a DMA of some type to be able to move data around in an unattended fashion. Indeed, I tend to use the debug interface to both interact with memory, peripherals, and the CPU: resetting, starting/stopping the CPU, stepping the CPU, and reading/writing CPU registers. That should give you all the more reason to get started with a crossbar early on.
In some of my early CPU tests, one of my earlier instruction fetches would just keep reading up to 16 instructions ahead of time. I thought this was great until I started examining the resulting performance. The first problem was that it wouldn't release the bus for either a data load or store, and the next problem was that the request was so long the result was often irrelevant by the time it arrived since the CPU had already branched away from the addresses it was fetching.
When I originally built the ZipCPU, it was designed for Wishbone only. I've now been discovering the need for an AXI front-end to the ZipCPU and finding that it's just as good (if not better) to expose a custom bus interface from the core of the CPU to the bus-dependent portion of the CPU. That way I can just rewrite the I&D bus handlers and wrappers independent of the CPU. Even better, I can separate the verification tasks of the memory components from that of the core CPU and then verify them independently.