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The next key to understanding AXI4 (same as AXI-full) is to understand how AXI addressing works. What are FIXED, INCR, and WRAP addressing modes, and how do they work? Xilinx's demo only ever handled INCR and WRAP addressing as I recall, and then only did it right if the beat size matched the bus size. You can find a more complete discussion on AXI addressing here. The component built in that blog article has since been optimized some more, but I still use it in all of my AXI4 (full) slave designs--it just makes handling addressing easy. You can find a recent copy of my optimized version here.
I've posted quite a few AXI designs on github. These include an AXI Crossbar, an AX DMA, and even an AXI scatter-gather based DMA. Some of my recent postings even include instruction or [data](instruction caches.